Mezzanine Memory Cell Structure for Higher-Density BEOL Memory
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing memory size without compromising performance, as larger memory sizes lead to increased die size, lower yields, and higher costs, while existing design rules for metallization layers restrict the integration density and efficiency of memory devices.
Innovation Solution
The implementation of a mezzanine memory cell structure using BEOL processes, which forms memory cells with larger, lower resistance interconnects and varying gate oxide thicknesses and channel dimensions, allowing for vertically stacked memory cells with optimized access time and power usage, and the use of multiple metallization layers to connect semiconductor dies and terminals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory size is increased using conventional metallization layers, then memory capacity improves, but die size increases and manufacturing yield decreases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertically stacked memory cells, utilizing the third dimension (height) to increase memory capacity without expanding die area. Multiple memory cells are stacked above each other, connected through vertical interconnects, thereby achieving higher integration density while maintaining manageable die size and improving manufacturing yield.
Solution Approach 2:
The memory device is divided into multiple discrete stacked memory cell units, each with its own gate layer, channel, and interconnect structure. This segmentation allows for modular fabrication and testing, improving manufacturing yield by enabling defect isolation and reducing the impact of failures in individual cells on the entire memory array.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision requirements increase
Solution Approach 1:
By stacking memory cells vertically, the patent achieves higher integration density without further reducing lateral feature sizes. This approach maintains relaxed manufacturing precision requirements for photolithography and patterning processes while still increasing the number of memory cells per die through vertical stacking.
Solution Approach 2:
The patent varies gate oxide thickness and channel dimensions as key parameters to optimize device performance and enable vertical stacking. By adjusting these parameters across different stacked levels, the design achieves high integration density while maintaining manufacturability with existing precision capabilities.
3Reliability
If metallization layer design rules are made more restrictive, then signal integrity improves, but interconnect efficiency and access time worsen
Solution Approach 1:
The patent applies different interconnect designs and materials to different regions and levels of the stacked memory structure. Shorter, lower-resistance interconnects are used for critical vertical paths, while other regions use conventional designs. This localized optimization maintains signal integrity where needed while minimizing access time for data retrieval operations.
Solution Approach 2:
By moving interconnects to multiple vertical levels and using three-dimensional routing, the patent reduces the length and resistance of critical signal paths. The vertical stacking enables shorter horizontal interconnect distances while maintaining signal integrity through proper layer isolation and shielding.
4Quantity of substance
If die size is increased to accommodate larger memory, then memory capacity improves, but manufacturing cost increases
Solution Approach 1:
The vertical stacking architecture enables high memory capacity in a compact die footprint, avoiding the cost increase associated with larger die sizes. By utilizing the vertical dimension, the patent achieves greater storage capacity without proportionally increasing die area, thereby maintaining cost-effectiveness.
Solution Approach 2:
The patent employs composite material structures including multiple gate oxide thicknesses, varied channel materials, and stacked interconnect layers to optimize device performance and manufacturing efficiency. These composite structures enable high-capacity memory cells to be fabricated using existing process technologies, avoiding the need for expensive new manufacturing capabilities.
Data Source
AI summary
A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.