3D Ferroelectric Memory Device Low Voltage Operation
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Solution Overview
Problem
Two-dimensional memory arrays are reaching scaling limits, and three-dimensional memory arrays face challenges with high voltages required for program and erase operations, slow speeds, and high power consumption due to low tunneling currents.
Innovation Solution
A metal-ferroelectric-insulator-semiconductor (MFIS) memory device is developed, where a ferroelectric layer replaces the silicon nitride layer, allowing for reduced program and erase voltages and increased speeds by screening electric fields differently based on polarity states, eliminating the need for carrier tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory arrays use conventional tunneling mechanisms for program and erase operations, then memory density can be increased, but high voltages are required and power consumption increases
Solution Approach 1:
The patent changes the fundamental operating mechanism from carrier tunneling to ferroelectric polarization switching. This parameter change allows program and erase operations to occur at low voltages (less than 5 volts) while maintaining high memory density through the three-dimensional stacked architecture. The ferroelectric layer's ability to maintain polarization states enables non-volatile storage without requiring high voltage tunneling.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including ferroelectric material layers, tunnel barrier layers, and semiconductor layers. This composite architecture enables the device to achieve both high density and low power consumption by combining the advantages of ferroelectric materials (low voltage switching) with tunnel barrier structures (charge trapping capability) in a three-dimensional configuration.
2Reliability
If three-dimensional memory arrays use carrier tunneling for program and erase operations, then data can be stored, but operation speeds are slow
Solution Approach 1:
The patent transitions from slow carrier tunneling processes to fast ferroelectric polarization switching. The ferroelectric material can switch polarization states almost instantaneously when a voltage threshold is exceeded, enabling program and erase operations to complete in less than 100 nanoseconds while maintaining reliable data storage through the stability of ferroelectric polarization states.
3Quantity of substance
If three-dimensional memory arrays are implemented to increase memory density, then scaling limits of two-dimensional arrays are overcome, but high voltages are required for operation
Solution Approach 1:
The patent fundamentally changes the operating parameter from high voltage tunneling to low voltage ferroelectric switching. The three-dimensional stacked structure maintains high memory density while the ferroelectric mechanism enables program and erase operations at voltages less than 5 volts, eliminating the need for high voltage stress required by conventional tunneling-based 3D memory.
4Ease of manufacture
If conventional memory structures are used, then manufacturing processes are established, but scaling limits are reached
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional stacked architectures. This dimensional change allows continued scaling and density improvement by utilizing the vertical dimension, stacking multiple memory layers above a substrate. The ferroelectric-based 3D structure maintains compatibility with established semiconductor manufacturing processes while achieving higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MFIS memory device achieves reduced program and erase voltages to less than 5 volts and speeds of less than 100 nanoseconds, significantly lowering power consumption while maintaining high memory density and reliability.
Implementation Method 1
a ferroelectric layer replaces the silicon nitride layer, allowing for reduced program and erase voltages and increased speeds by screening electric fields differently based on polarity states
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.