MFMIS Memory Cell Integration With CMOS for Stable Memory Window
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Solution Overview
Problem
The integration of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory cells with complementary metal-oxide semiconductor (CMOS) transistors poses challenges due to variability in the fabrication process and the need for reliable memory window tuning.
Innovation Solution
The proposed integrated circuit (IC) structure includes an MFMIS memory cell with an additional metal layer between the ferroelectric and insulator layers, integrated alongside a CMOS transistor on a semiconductor substrate, utilizing trench isolation and polysilicon electrodes to decouple program/erase and read paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional metal layer is added to form MFMIS memory cell, then reliability and memory window are improved, but fabrication variability and process complexity increase
Solution Approach 1:
The patent introduces an additional metal layer as an intermediary between the ferroelectric layer and the insulator layer. This intermediate metal layer serves as a buffer that decouples the fabrication processes, allowing independent optimization of the ferroelectric and insulator layers without direct interface variability. The intermediate layer acts as a mediator that absorbs process variations and enables better control over the overall device characteristics.
Solution Approach 2:
The gate stack is segmented into distinct functional layers with the additional metal layer creating separate zones for ferroelectric operation and insulator stability. This segmentation allows independent fabrication and optimization of each layer, reducing the cumulative variability that would exist in a directly interfaced MFIS structure. The segmented architecture enables separate process control for depositing the ferroelectric material and the insulator material.
2Adaptability or versatility
If MFMIS memory cell is integrated with CMOS transistor, then functionality is improved, but integration challenges and manufacturing difficulty increase
Solution Approach 1:
The additional metal layer in the MFMIS structure serves multiple functions: it acts as an electrode for the ferroelectric capacitor, provides a stable interface for the insulator layer, and enables independent biasing for program/erase and read operations. This multi-functionality consolidates several requirements into a single structural element, simplifying the overall integration with CMOS transistors while maintaining enhanced functionality.
Solution Approach 2:
The intermediate metal layer serves as a mediator that enables independent control of the ferroelectric and insulator components during integration with CMOS circuitry. This intermediate structure allows for separate routing and biasing schemes for program/erase operations versus read operations, facilitating easier integration with standard CMOS processes without requiring complex shared control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variability, enhances reliability, and increases the memory window of MFMIS memory cells, allowing for multi-bit operation and improved endurance compared to traditional MFIS memory cells, while also lowering production costs.
Implementation Method 1
The polarization of the ferroelectric material is retained and can be controlled by the electric field applied between the gate and the channel
Implementation Method 2
a trench isolation separating the MFMIS memory cell and the CMOS transistor
Data Source
AI summary
An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.