MFMIS Memory Cell With Internal Gate Electrode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional (3D) memory arrays face challenges in achieving high memory density and reliability due to the low electric field across the ferroelectric layer and high electric field across the gate dielectric layer in MFIS memory cells, leading to weak polarization switching, small memory window, high power consumption, and degradation of the gate dielectric layer.
Innovation Solution
The introduction of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device with an internal gate electrode, allowing for different capacitor areas for the ferroelectric and gate dielectric layers, which are tuned during formation by adjusting the dimensions of the control and internal gate electrodes and semiconductor channel, to achieve a high electric field across the ferroelectric layer and a low electric field across the gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MFIS memory cell structure is used, then the device is simple to manufacture, but the electric field across the ferroelectric layer is low leading to weak polarization switching
Solution Approach 1:
The memory cell is divided into two separate capacitor structures: a ferroelectric capacitor with control gate electrode and ferroelectric layer, and a gate dielectric capacitor with gate dielectric layer. This segmentation allows independent optimization of each capacitor's electric field characteristics, enabling strong polarization switching in the ferroelectric layer while maintaining reliable operation of the gate dielectric layer.
Solution Approach 2:
Different regions of the memory cell are assigned different functions and material properties. The ferroelectric layer region is optimized for high electric field to enable strong polarization switching, while the gate dielectric layer region is optimized for low electric field to ensure reliability and prevent degradation. This local differentiation of quality allows each component to operate under optimal conditions.
2Reliability
If the gate dielectric layer is thin to reduce capacitance, then the memory window is improved, but the gate dielectric layer degrades due to high electric field
Solution Approach 1:
The harmful high electric field stress is extracted from the gate dielectric layer by separating the gate dielectric capacitor from the ferroelectric capacitor. The gate dielectric layer is now part of a separate capacitor structure that can be independently designed with appropriate dimensions and materials to withstand the required electric fields without degradation.
Solution Approach 2:
The internal gate electrode acts as an intermediary element that couples the two capacitor structures while allowing independent optimization. It enables the ferroelectric capacitor to have high electric field for strong polarization switching while the gate dielectric capacitor can have lower electric field for reliable operation, mediating between the conflicting requirements.
3Quantity of substance
If the ferroelectric layer is thick to increase capacitance, then the memory density is improved, but the polarization switching becomes weaker due to low electric field
Solution Approach 1:
The capacitor area of the ferroelectric capacitor is increased by expanding the control gate electrode and ferroelectric layer dimensions, while the capacitor area of the gate dielectric capacitor is adjusted separately. This parameter change allows the ferroelectric layer to have sufficient capacitance for high memory density while maintaining high electric field for strong polarization switching, as the two capacitors are independently optimized.
4Quantity of substance
If 3D memory arrays are implemented to increase memory density, then the storage capacity is improved, but the manufacturing complexity and reliability challenges increase
Solution Approach 1:
The 3D memory array is constructed by stacking multiple MFIS memory cells vertically, with each cell containing separate ferroelectric and gate dielectric capacitors. This segmentation allows independent optimization of each layer's electric field characteristics while maintaining the benefits of 3D stacking for high memory density, reducing the manufacturing complexity compared to monolithic 3D structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the endurance and retention of the MFMIS memory cell by improving polarization switching, reducing power consumption, and increasing the reliability of the gate dielectric layer.
Implementation Method 1
the ferroelectric layer switches between a first polarization state and a second polarization state in response to an applied electric field
Implementation Method 2
a gate dielectric layer between the internal gate electrode and the semiconductor channel, a control gate electrode on an opposite side of the internal gate electrode as the semiconductor channel and uncovered by the second source/drain region, a ferroelectric layer between the control gate electrode and the internal gate electrode
Data Source
AI summary
Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.