MFND Controller FIFO Buffering for Fair, Consistent NVMe Arbitration
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Solution Overview
Problem
In Multi-Function NVMe Devices (MFNDs), the lack of knowledge about the content of upcoming commands hinders effective arbitration and results in suboptimal quality of service (QoS), fairness, and consistency in sharing SSD resources across multiple virtual machine tenants.
Innovation Solution
Implementing a first-in-first-out (FIFO) mechanism per submission queue within the device controller to hold the head of submission queues, combined with a second arbiter that schedules commands based on the content of these queues, allowing for informed decision-making during arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the device controller directly fetches commands from host submission queues without internal buffering, then the device complexity is reduced, but the arbitration quality and knowledge of next command content deteriorates
Solution Approach 1:
The device controller performs preliminary action by fetching and buffering next commands from host submission queues into internal device-side queues before arbitration occurs. This allows the arbiter to have advance knowledge of command content, priorities, and types, enabling informed arbitration decisions while maintaining a relatively simple overall device structure.
2Reliability
If the device buffers next commands in internal device-side queues, then the arbitration quality and QoS improves, but the device complexity increases
Solution Approach 1:
The device controller is segmented into distinct functional components: a command fetching module that populates device-side queues, and a separate arbiter module that consumes from these queues. This segmentation allows the buffering functionality to be added without overwhelming the overall device complexity, as each component has a specific, well-defined role.
Solution Approach 2:
Device-side queues serve as an intermediary buffer between the host submission queues and the arbitration logic. This intermediary structure decouples the fetching operation from the arbitration operation, allowing the arbiter to make informed decisions based on buffered command information without directly accessing host memory, thus improving QoS while managing complexity.
3Measurement precision
If multiple arbiters are used for different arbitration stages, then the arbitration precision and resource allocation improves, but the device complexity increases
Solution Approach 1:
The arbitration process is segmented into multiple stages with different arbiter modules: a first arbiter for initial command selection and a second arbiter for refined resource allocation. Each arbiter focuses on specific arbitration dimensions, improving overall precision while keeping individual arbiter logic relatively simple and modular.
Data Source
AI summary
Contents of the next commands are considered as part of an arbitration between virtual functions (VFs). The device controller will hold the head of the submission queues (SQ) internally. The controller is able to do so by implementing a small first in first out (FIFO) per submission queue. The second arbiter and the main arbiter, which is responsible for the command scheduling, fetches the commands from the internal small FIFO. Using this technique, the second arbiter gains visibility of the next commands that participate in the arbitration since the next commands are held internally and not in host memory.