MICE CMOS Logic Layout for Heavy-Ion Multinode Upset Immunity
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Solution Overview
Problem
Modern CMOS circuit designs face challenges in immunity to heavy-ion induced single-event upsets and transients due to increased susceptibility with smaller feature sizes and higher design density, making existing hardening techniques impractical for effective mitigation in true space environments.
Innovation Solution
The implementation of a logic family with isolated nodes and redundant datapaths, utilizing three identical PMOS and NMOS transistors with isolation devices between each connecting node, and additional isolation devices between logic functions to prevent error propagation and ensure correct logic state recovery after a heavy-ion strike.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit feature sizes are reduced to increase design density and performance, then circuit performance and density improve, but susceptibility to heavy-ion induced upsets increases
Solution Approach 1:
The circuit nodes are segmented into isolated groups with physical separation and isolation devices (such as isolation transistors or resistors) between them. This segmentation prevents charge deposition from a single ion strike from affecting multiple nodes simultaneously, thereby maintaining high circuit density while reducing upset susceptibility through spatial division.
Solution Approach 2:
Isolation devices are introduced as intermediary elements between circuit nodes. These intermediaries (isolation transistors, resistors, or protective structures) act as buffers that prevent direct coupling of charge effects between adjacent nodes, allowing the circuit to maintain high density while the intermediaries block the propagation of upset signals.
2Area of stationary object
If more transistors are placed in a smaller region to increase design density, then circuit density improves, but the ease of mitigating upsets worsens
Solution Approach 1:
The dense transistor region is segmented into isolated functional blocks with deliberate spacing and isolation devices between them. This segmentation strategy allows high transistor density within each block while the isolation structures prevent upset propagation, making radiation hardening achievable even in high-density configurations.
Solution Approach 2:
Different regions of the circuit are assigned different qualities: critical nodes receive enhanced isolation and protection structures, while non-critical regions use standard density. This local differentiation allows the circuit to achieve high overall density while providing targeted upset mitigation where it matters most.
3Ease of manufacture
If standard CMOS fabrication processes are used without modifications, then manufacturing ease improves, but immunity to heavy-ion upsets worsens
Solution Approach 1:
The isolation devices and protective structures are designed to be compatible with standard CMOS fabrication processes, using the same transistor types and materials already present in the process. This allows the circuit to gain radiation hardening capabilities without requiring specialized fabrication steps, maintaining manufacturing simplicity while improving upset immunity.
Data Source
AI summary
This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques.