Micro-Array LED Pixel Spacing via Self-Aligned Isolation
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Solution Overview
Problem
The existing methods for manufacturing micro-array light emitting diodes result in a wide dark region between pixels due to increased distance caused by n-type electrodes and misalignment during mask alignment, leading to reduced light intensity and visibility.
Innovation Solution
A method involving the formation of p-type electrodes and isolation parts on a semiconductor lamination structure in a self-aligning manner, using p-type electrodes as masks, and etching or increasing electrical insulation of the p-type semiconductor layer to minimize the interval between light emitting pixels, with the n-type electrode acting as a common electrode outside the emission area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an n-type electrode is formed between the light emitting pixels to stably supply current, then current supply stability is improved, but the distance between the light emitting pixels increases, resulting in a wider dark region
Solution Approach 1:
The patent extracts the n-type electrode from the region between light emitting pixels and relocates it to the peripheral region only. This removes the harmful effect of the electrode increasing the distance between pixels while maintaining its useful function of supplying current. The isolation part is introduced to electrically isolate the peripheral n-type electrode from the active region, achieving both current supply stability and minimized pixel spacing.
2Manufacturing precision
If the mask is aligned with accuracy of micrometers to isolate the semiconductor lamination structure, then isolation precision is improved, but it becomes difficult to align the mask and the interval between pixels is widened due to margin requirements
Solution Approach 1:
The patent employs self-aligned isolation formation where the isolation part is formed using the p-type electrode pattern as a reference. This self-alignment mechanism eliminates the need for complex mask alignment procedures, reducing both alignment difficulty and the need for large margins. The isolation part automatically positions itself relative to the light emitting pixels, achieving high precision without increasing manufacturing complexity.
3Manufacturing precision
If the active layer and portions of n-type and p-type semiconductor layers are etched to isolate the semiconductor lamination structure, then isolation is achieved, but the interval between the plurality of light emitting pixels is widened
Solution Approach 1:
The patent applies local quality by forming the isolation part only in the peripheral region between light emitting pixels, not in the active emission regions. The isolation part is localized to where it is needed for electrical isolation, while the active layers are preserved in the emission regions. This selective isolation maintains pixel spacing while achieving effective isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the dark region between pixels, enhancing light intensity and visibility by minimizing the interval between light emitting pixels and stabilizing power supply to each pixel, while reducing the overall size of the micro-array light emitting diode.
Implementation Method 1
at least one of ion implantation, plasma treatment, or E-beam irradiation may be performed
Implementation Method 2
at least one of ion implantation, plasma treatment, or E-beam irradiation may be performed
Implementation Method 3
at least one of ion implantation, plasma treatment, or E-beam irradiation may be performed
Data Source
AI summary
The present invention suggests a method for manufacturing a micro-array light emitting diode comprising: a step for forming a semiconductor lamination structure by stacking an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate; a step for forming a plurality of p-type electrodes so as to be arranged two-dimensionally apart from each other on the p-type semiconductor layer; and a step for forming an isolation part in the p-type semiconductor layer exposed between the plurality of p-type electrodes in a self-aligning manner.