Micro-bump Test Circuit for Stacked Semiconductor Connectivity
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Solution Overview
Problem
Current semiconductor technologies face challenges in effectively testing the connectivity and performance of micro-bumps in stacked semiconductor devices, particularly in three-dimensional structures, where the high density and complexity of micro-bumps make traditional testing methods inefficient and difficult.
Innovation Solution
A semiconductor device is designed with a combination of normal micro-bumps for regular operations and test micro-bumps, along with a test circuit that forms a serial scan chain to store, apply, and feedback signals, allowing for the evaluation of both normal and test micro-bumps' connectivity through dedicated pads and bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional testing methods are used for micro-bumps in stacked semiconductor devices, then the testing process is simpler, but the testing efficiency and accuracy deteriorate due to high density and complexity of micro-bumps
Solution Approach 1:
The patent divides the micro-bump testing into separate functional groups: normal micro-bumps for regular operations and test micro-bumps for connectivity verification. This segmentation allows dedicated test circuits to target specific bump types, improving testing efficiency without being overwhelmed by the overall complexity of the high-density micro-bump structure
Solution Approach 2:
The patent introduces test micro-bumps as intermediary elements that facilitate connectivity verification between stacked semiconductor chips. These test micro-bumps act as mediators that enable indirect testing of through-electrode connections, allowing test signals to traverse the vertical stack and return feedback without requiring direct access to internal connection points
2Reliability
If dedicated test micro-bumps and test circuits are added, then the connectivity verification capability is improved, but the device complexity increases
Solution Approach 1:
The test circuits are designed with multi-functionality, serving both normal operational testing and connectivity verification through through-electrodes. The scan cells and serial scan chains can operate in different modes: applying test patterns to micro-bumps and analyzing feedback signals. This universal design improves reliability without proportionally increasing complexity, as the same circuit infrastructure serves multiple purposes
Solution Approach 2:
The patent merges the test micro-bumps and test circuits into the existing stacked semiconductor device architecture. Rather than adding completely separate testing infrastructure, the test elements are integrated alongside normal micro-bumps and operational circuits, allowing connectivity verification to be performed as part of the device's normal test sequence
3Productivity
If high density micro-bumps are used for three-dimensional stacking, then the integration performance is improved, but the testing difficulty increases
Solution Approach 1:
The patent implements feedback mechanisms where test signals applied to test micro-bumps traverse through through-electrodes and return feedback signals that indicate connection status. The scan cells capture and store these feedback signals, which are then sequentially output for analysis. This feedback loop enables automatic verification of connectivity in high-density stacks without requiring manual inspection or complex external testing equipment
Solution Approach 2:
The patent transitions from two-dimensional planar testing to three-dimensional vertical testing by utilizing the stacked architecture itself. Test signals propagate through the vertical dimension via through-electrodes connecting multiple chip layers, allowing connectivity verification in the depth dimension rather than only on the surface plane. This dimensional approach matches the high-density integration strategy
Data Source
AI summary
A semiconductor device includes a plurality of first micro-bumps suitable for transferring normal signals; a plurality of a second micro-bumps suitable for transferring test signals; and a test circuit including a plurality of scan cells respectively corresponding to the first and second micro-bumps. The test circuit is suitable for applying signals stored in the respective scan cells to the first and second micro-bumps, feeding back the applied signals from the first and second micro-bumps to the respective scan cells, and sequentially outputting the signals stored in the scan cells to a test output pad.