Micro-Device Bonding with 3D Nanostructures for Fine Pixel Pitch
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Solution Overview
Problem
Existing bonding technologies for micro-devices face challenges in achieving reliable and efficient bonding, particularly with decreasing pixel pitch, where surface area and structural mismatch issues lead to reduced yield and reliability.
Innovation Solution
The formation of conductive, flexible, and thermally stable 2D and 3D nanostructures on substrates, using techniques such as nanotexturing, nanoporous structures, and self-assembly, to enhance bonding area and interlocking capabilities between micro-device substrates, with controlled temperature and pressure during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding technologies are used for micro-devices with decreasing pixel pitch, then bonding process simplicity is maintained, but bonding yield and reliability deteriorate due to surface area and structural mismatch issues
Solution Approach 1:
The patent transitions from conventional 2D planar bonding interfaces to 3D nanostructured bonding surfaces. By forming vertical nanowires, nanopillars, or nanotubes on the bonding pads, the bonding interface extends into the third dimension, dramatically increasing the effective bonding area and improving yield without complicating the overall device structure
Solution Approach 2:
The patent employs porous or textured nanostructured surfaces (nanowire arrays, nanopillar forests, or nanotube bundles) on bonding pads. These porous/nanostructured surfaces increase surface area through factor of 10x or more compared to planar surfaces, enabling reliable bonding even when pixel pitch decreases and bonding area is constrained
2Reliability
If bonding area is increased using nanostructures, then bonding reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes self-assembly mechanisms where nanowires, nanopillars, or nanotubes spontaneously form ordered arrays through controlled chemical or physical processes. This self-organizing behavior eliminates the need for complex lithographic patterning and alignment steps, significantly simplifying manufacturing while achieving high-density nanostructured bonding surfaces
Solution Approach 2:
The patent controls nanostructure formation by adjusting key parameters such as material composition, deposition temperature, etch conditions, or chemical vapor deposition ratios. By optimizing these parameters, the desired nanostructure morphology (nanowires, nanopillars, or nanotubes) is achieved through conventional semiconductor manufacturing processes without requiring additional fabrication steps
3Productivity
If pixel pitch is decreased for high-density micro-device arrays, then device integration density improves, but bonding effectiveness deteriorates due to reduced surface area
Solution Approach 1:
By forming vertical nanostructures (nanowires extending upward, nanopillars rising from the surface, or nanotubes standing erect), the bonding area is no longer limited to the planar footprint defined by pixel pitch. The vertical dimension provides additional bonding area that scales independently of pixel pitch reduction, enabling high-density integration while maintaining effective bonding area
Solution Approach 2:
The bonding pad surface is segmented into numerous discrete nanostructures (individual nanowires, nanopillars, or nanotubes) rather than a continuous planar surface. This segmentation allows each nanostructure to contribute to bonding independently, and the collective effect of many segmented elements provides robust bonding even when the overall pad area is reduced for higher pixel density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the bonding yield and reliability by increasing the surface area and mechanical stability, enabling effective electrical conductivity and thermal stability between substrates, even with high-density micro-device arrays.
Implementation Method 1
the surface area and structural mismatch issues lead to reduced yield and reliability
Implementation Method 2
increasing the surface area and mechanical stability, enabling effective electrical conductivity and thermal stability between substrates
Implementation Method 3
enabling effective electrical conductivity and thermal stability between substrates
Implementation Method 4
enabling effective electrical conductivity and thermal stability between substrates
Data Source
AI summary
This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.