Micro Display 3DIC Bonding Layout for Compact AR/VR Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for fabricating display devices for augmented reality (AR) and virtual reality (VR) applications face challenges due to the use of long wires and metal interconnections, which consume space and complicate mounting, particularly in smaller form factors.
Innovation Solution
A 3DIC approach is employed, utilizing a wafer with distinct areas for bonding pads made of different materials and pitches, allowing for the integration of display driver integrated circuits (DDICs) with reduced size and cost through hybrid bonding and packaging, using a silicon substrate with defined areas for connecting external circuits, LV devices, and micro displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then the connection reliability is improved, but the device size and mounting complexity increase
Solution Approach 1:
The patent transitions from planar 2D connections to 3D vertical stacking architecture. Multiple functional layers (display module, DDICs, timing controller) are stacked vertically and interconnected through through-silicon vias (TSVs), enabling short vertical interconnections that replace long horizontal wires, thus reducing device area while maintaining connection reliability
Solution Approach 2:
The patent implements a nested structure where DDICs are embedded within the display module stack, and timing controllers are integrated into the same 3D structure. This nesting eliminates external connections and reduces the overall device footprint while ensuring reliable internal connections
2Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then the connection reliability is improved, but the mounting difficulty increases
Solution Approach 1:
The patent merges the display module, DDICs, and timing controller into a single integrated 3D stack structure. This consolidation eliminates separate mounting operations and complex wire bonding processes, simplifying the manufacturing workflow while ensuring reliable integrated connections
Solution Approach 2:
By moving to vertical 3D integration with TSV interconnections, the patent enables automated stacking and bonding processes that are simpler than manual wire routing and mounting, thereby improving ease of manufacture while maintaining connection reliability
3Adaptability or versatility
If different materials are used for bonding pads in different areas, then the bonding compatibility is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies different materials to bonding pads in specific locations based on their functional requirements. For example, copper bonding pads are used in certain areas while aluminum or other materials are used in different areas, optimizing bonding compatibility for each specific connection interface without requiring complete redesign of the entire structure
Solution Approach 2:
The wafer is divided into distinct areas (first area, second area, third area) with different bonding pad materials and pitches. This segmentation allows each area to be optimized for its specific bonding requirements while maintaining overall process integration, managing manufacturing complexity through systematic regional differentiation
Data Source
AI summary
A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.