In-situ Micro-Feature Heat Spreader for Coreless Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current coreless bumpless build-up layer (BBUL-C) package architectures require additional manufacturing steps and costs due to the need for a heat spreader attachment post-packaging, which is time-consuming and costly, and are inadequate for larger dies with higher power consumption where thermal cooling is a significant challenge.
Innovation Solution
The method involves forming a cavity in a copper foil carrier material, attaching a die within the cavity, forming dielectric material and interconnects, and patterning the carrier to create micro-feature structures that serve as an in-situ heat spreader, reducing the need for post-manufacturing heat spreader attachment and enabling efficient thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a heat spreader is attached post-package manufacturing, then thermal management is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent merges the heat spreader function with the carrier substrate by forming copper-rich micro-feature structures directly on the carrier during the package manufacturing process. This eliminates the need for a separate heat spreader attachment step, reducing manufacturing complexity while maintaining effective thermal management.
Solution Approach 2:
The heat dissipation structures are formed preliminarily during the package build-up process on the carrier substrate. The copper foil is patterned and etched to create heat-spreading micro-features before the die is attached and before package completion, thereby eliminating post-manufacturing attachment steps.
2Ease of manufacture
If copper foil is etched off after package separation from core, then coreless package structure is achieved, but heat dissipation capability is reduced
Solution Approach 1:
The patent applies local quality by creating copper-rich micro-feature structures in specific locations on the carrier substrate where heat dissipation is needed. Instead of uniformly removing all copper, the etching process is selectively applied to retain copper in areas that will form heat-spreading features adjacent to the die.
Solution Approach 2:
The patent converts the normally discarded copper foil into a beneficial heat dissipation structure. The copper that would otherwise be etched off and wasted is instead patterned to form micro-feature structures that actively manage thermal energy, turning a waste material into a functional thermal management component.
3Power
If larger dies with higher power consumption are used, then processor performance is improved, but thermal management challenges increase
Solution Approach 1:
The patent creates localized copper-rich micro-feature structures directly adjacent to and beneath the die footprint, concentrating thermal management resources where they are most needed. This local concentration of heat-spreading material effectively manages the thermal challenges of high-power dies without requiring uniform thermal management across the entire package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by half, enhances heat dissipation, and allows for the creation of effective micro-channel cooling solutions, addressing thermal challenges in larger, higher power consumption dies, while improving throughput and reliability.
Implementation Method 1
patterning the carrier to create micro-feature structures that serve as an in-situ heat spreader, reducing the need for post-manufacturing heat spreader attachment and enabling efficient thermal management
Data Source
AI summary
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.