Micro-Gating Clock Buffer for Independent Clock Domain Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock gating techniques in synchronous digital systems lead to unnecessary power consumption and heat dissipation due to multiple clock domains being turned on and off together, despite some domains being unused, and the increasing complexity of clock networks with technology scaling.
Innovation Solution
Implementing a power saving micro-gating clock buffer with a local clock buffer that uses a single enable capture latch and micro-gating logic to independently control multiple clock domains, reducing power consumption by selectively turning on and off clock domains using a common latch and micro-gating logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock gating techniques are used to turn off unused clock domains, then power consumption is reduced, but multiple clock domains are turned on and off together even when some are unused, leading to unnecessary power consumption and heat dissipation
Solution Approach 1:
The patent segments the clock gating control into two levels: a coarse-grain enable signal that controls the overall clock buffer and a fine-grain micro-gating signal that independently controls each clock domain. This segmentation allows individual domains to be turned off without affecting others, reducing unnecessary power consumption while maintaining manageable complexity through hierarchical control structure.
Solution Approach 2:
The patent adds a new dimension to clock gating by introducing micro-gating logic that operates at the clock domain level within each buffered domain. This creates a two-dimensional control space (buffer enable + domain micro-gating) that enables finer power management without proportionally increasing overall system complexity.
2Adaptability or versatility
If multiple latches are used to capture enable signals for each clock domain, then independent control of each domain is achieved, but the number of latches and circuit complexity increases
Solution Approach 1:
The patent makes a single latch multi-functional by using it to capture the master enable signal that controls the entire clock buffer. This single latch serves all clock domains simultaneously, eliminating the need for multiple dedicated latches while still enabling independent domain control through the micro-gating logic that operates on the buffered clock signal.
Solution Approach 2:
The patent merges the enable signal capture function into a single shared latch rather than having separate latches for each domain. The micro-gating logic then combines the buffered clock signal with individual domain enable signals to achieve independent control, reducing the total number of latches while maintaining versatility.
3Reliability
If clock signals are continuously supplied to all clock domains, then system reliability is maintained, but power consumption increases due to unnecessary switching in unused domains
Solution Approach 1:
The patent implements periodic action by using the buffered clock signal that is enabled only when needed. The micro-gating logic applies the buffered clock periodically to each domain based on its enable signal, ensuring that clock switching occurs only in active domains during their required time periods, thus maintaining reliability while reducing power consumption in inactive domains.
Data Source
AI summary
A local clock buffer for improved energy efficiency using a power saving micro-gating clock buffer includes a grid node configured to receive a global clock signal from a global clock grid; an enable gate configured to output a master enable signal based on respective values of two or more enable signals; an enable signal capture latch configured to store a value of the master enable signal; a clock gate configured to output, in dependence upon the stored value of the master enable signal, a pulsed clock signal based on the global clock signal; and micro-gating logic configured to: receive the pulsed clock signal and the two or more enable signals; and output two or more local clock signals using the pulsed clock signal, wherein each local clock signal is selectively output based on a value of one of the two or more enable signals.