Micro Interconnect Structures for Edge-to-Edge Semiconductor Dies
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Solution Overview
Problem
Existing semiconductor devices face challenges in minimizing the dedicated edge space required for interconnects between semiconductor die, which limits the active die area and increases the overall footprint of the semiconductor package.
Innovation Solution
The method involves forming inter-die interconnects between side-by-side semiconductor die with contacting side surfaces, using conductive layers and precision plasma etching to create extensions and recesses on the side surfaces, allowing for direct physical contact and minimal electrical interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bond wire is used for interconnect between semiconductor die, then electrical connection is established, but dedicated edge space and separation distance are required increasing package footprint
Solution Approach 1:
The patent merges the interconnect function into the die edge structure itself by forming conductive extensions and recesses that directly contact adjacent dies. This eliminates the need for separate bond wires and reduces the required edge space, as the interconnect is integrated into the die structure rather than being a separate component.
Solution Approach 2:
The patent transitions from planar wire bonding to three-dimensional edge-to-edge contact. By forming conductive extensions protruding from die edges and matching recesses, the interconnect moves from a two-dimensional wire layout to a three-dimensional direct contact structure, reducing the horizontal space requirement.
2Area of stationary object
If dedicated edge space is reserved for scribe grid and die edge seal, then manufacturing reliability is improved, but active die area is reduced
Solution Approach 1:
The patent applies local quality by differentiating the treatment of die edges: some edges form conductive extensions for interconnect while other edges maintain traditional sealing structures. This allows the interconnect function to be implemented in specific locations without compromising the reliability functions of other die edges.
Solution Approach 2:
The patent segments the die edge into functional zones: interconnect regions with conductive extensions and recesses, and separate regions for scribe grid and die edge seal. This segmentation allows each function to be optimized independently, maximizing active area while maintaining manufacturing reliability.
3Ease of manufacture
If through silicon vias (TSVs) are used for inter-die interconnect, then vertical interconnection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent uses a simpler, less expensive interconnect structure compared to TSVs. The conductive extensions and recesses can be formed using standard semiconductor fabrication processes without requiring the complex TSV formation steps, making it a more cost-effective solution for inter-die interconnection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the semiconductor package dimensions and cost, increases the efficiency of the footprint, and provides low inductance and resistance compared to traditional wire bonding methods.
Implementation Method 1
precision plasma etching to create extensions and recesses on the side surfaces
Data Source
AI summary
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.