Micro Interconnect Structures for Edge-Joined Semiconductor Dies

The patent merges the interconnect function directly into the die edge structure by forming conductive layers and interlocking features (extensions and recesses) on the die edges themselves. This eliminates the need for separate wire bonds and dedicated edge space, as the interconnect structure is integrated into the die geometry. The conductive layers are formed on the active surface and extend to the edges, where they interlock with adjacent dies through precisely formed extensions and recesses.

The patent transitions from planar wire bonding (2D approach) to three-dimensional edge interlocking (3D approach). By forming extensions and recesses on the die edges that interlock vertically and laterally, the interconnect structure utilizes the third dimension (depth/height) to achieve connection without requiring additional lateral edge space. This dimensional transition allows the interconnect to be formed within the existing die footprint.

The patent segments the die edge into multiple functional zones: active circuit regions, interconnect extension regions, and interlocking feature regions. By dividing the edge space into these segments, the design optimizes each zone for its specific function while minimizing total edge space requirements. The conductive layers are segmented into different patterns (e.g., fingers, pads) that can be precisely positioned to maximize active area while ensuring reliable interconnection.

The interconnect structure is nested within the die edge geometry itself. The extensions and recesses are formed as integral parts of the die structure, with conductive layers nested within the die substrate and extending to the edges. This nesting approach allows the interconnect function to be embedded within the existing die form factor without adding external interconnect elements that would increase package footprint.

The extensions and recesses are formed as preliminary features during the die fabrication process itself, before the dies are packaged. The conductive layers are deposited and patterned on the die edges during front-end manufacturing, and the interlocking features are formed through standard semiconductor processing techniques. This preliminary formation of interconnect features eliminates the need for post-packaging alignment and bonding operations, simplifying the overall manufacturing process despite the precision requirements.

The die edges are designed to be self-aligning through the interlocking extensions and recesses. The precise geometric features automatically guide the alignment of adjacent dies during packaging, eliminating the need for complex external alignment mechanisms. The self-service nature of this approach allows standard packaging equipment to achieve precise alignment through the inherent geometry of the interlocking features, reducing manufacturing complexity.