Micro-LED Display Panel Bonding With Isolation-Layer Self-Alignment

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Solution Overview

Problem

The accuracy of bonding positions between Micro-LED chips and substrates in display panels is poor, leading to bonding failures due to limitations in alignment accuracy and lack of pressure control during the bonding process.

Innovation Solution

A manufacturing method for display panels involves forming isolation layers with specific openings for P-type and N-type electrodes, allowing for self-alignment and embedding these electrodes into bonding layers, which reduces lateral deviations and prevents short circuits by confining the bonding materials within the openings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional bonding methods are used without isolation layers, then the bonding process is simpler, but the bonding position accuracy is poor and bonding failure occurs

Engineering Contradiction:
Improvebonding position accuracyVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The bonding structure is segmented into distinct functional zones: isolation layers with openings define specific bonding regions, separating the bonding areas from non-bonding areas. This segmentation enables precise positioning of electrodes within defined openings, improving bonding accuracy while maintaining manageable structural complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation layers with pre-formed openings are created before the bonding process. These openings preliminarily define the exact positions where bonding should occur, guiding the electrode placement and ensuring accurate bonding positions before the actual bonding takes place, thereby improving manufacturing precision

Inventive Principle:
Principle #10Preliminary action

2Reliability

If alignment accuracy is not controlled during bonding, then the bonding process is faster, but bonding failure occurs due to lateral deviation

Engineering Contradiction:
Improvebonding reliabilityVSAvoidbonding process time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The isolation layers with openings provide self-alignment functionality during bonding. The openings automatically guide the electrodes to the correct positions through their predefined geometry, enabling the structure to self-correct alignment deviations without requiring external alignment equipment or complex control systems, thus improving reliability while maintaining efficient bonding speed

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If bonding materials are not confined, then the bonding process is simpler, but lateral deviation occurs and short circuits happen

Engineering Contradiction:
Improveelectrode positioning accuracyVSAvoidbonding structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The isolation layers provide different properties in different locations: openings are created only at specific locations where bonding is required, while other areas remain isolated. This local differentiation confines bonding materials to specific regions, ensuring precise electrode positioning and preventing short circuits, while the overall structure remains relatively simple through targeted rather than universal complexity

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250006858A1Display panel and manufacturing method thereof
Publication Date: 2025.01.02 XIAMEN UNIV
  • US20250006858A1 patent drawing
  • US20250006858A1 patent drawing
  • US20250006858A1 patent drawing

AI summary

The present application provides a display panel and a manufacturing method thereof, the manufacturing method comprises: providing a first substrate, wherein a side of the first substrate is provided with a plurality of Micro-LED chips that are spaced apart from each other; providing a second substrate, wherein a surface on a side of the second substrate has a plurality of conductive layer parts; forming an isolation layer on the second substrate, wherein the isolation layer has a plurality of opening groups, each of the opening groups comprises a first opening and a second opening to expose a surface of one of the conductive layer parts, wherein a width of the first opening is greater than that of a P-type electrode, and a width of the second opening is greater than that of a N-type electrode; forming a first bonding layer in the first opening and forming a second bonding layer in the second opening; while supporting the chip body by the isolation layer, bonding the P-type electrode with the first bonding layer and simultaneously bonding the N-type electrode with the second bonding layer, wherein the P-type electrode is embedded into the first bonding layer and the N-type electrode is embedded into the second bonding layer.