Micro LED Chip Thickness Ratio for Side Wall Defect Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Micro light emitting diode (μLED) chips with reduced area suffer from electron and hole transmission to side walls, leading to inefficient light emission due to defects and excessive semiconductor layer thickness absorbing light, which hampers high-resolution display performance.
Innovation Solution
The μLED chip design omits at least one semiconductor layer, such as a current-spreading layer, to achieve a thinner structure with a specific thickness ratio of semiconductor layers, reducing electron and hole transmission to side walls and enhancing light-emitting performance. This includes a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer with optimized thickness ratios and materials like carbon-doped gallium phosphide and aluminum indium phosphide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the area of μLED chip is reduced to achieve high resolution, then the display resolution is improved, but electron and hole are easily transmitted to side wall and combined in defect with no light emission
Solution Approach 1:
The patent extracts and removes the current-spreading layer from the traditional multi-layer semiconductor structure. This extraction eliminates the harmful current spreading effect that causes carriers to reach side walls, while maintaining the essential light-emitting function through the simplified three-layer structure (p-type layer, light-emitting layer, n-type layer).
Solution Approach 2:
The patent changes the thickness parameters of the semiconductor layers to achieve optimal performance. Specifically, the total thickness of all semiconductor layers is controlled to be 2-10 μm, with the p-type layer being 0.5-5 μm and the n-type layer being 0.5-5 μm. This parameter optimization prevents carrier overflow to side walls while maintaining efficient light emission.
2Illumination intensity
If the semiconductor layer thickness is increased to improve light emission, then the light emission capability is improved, but the overly-thick semiconductor layer absorbs light and efficiency becomes inferior
Solution Approach 1:
The patent optimizes the thickness parameters of semiconductor layers to balance light emission capability and light absorption loss. The total thickness is controlled at 2-10 μm, which is thick enough to provide sufficient light emission but thin enough to minimize self-absorption. The light-emitting layer thickness is specifically controlled at 0.1-2 μm to maximize emission efficiency.
Solution Approach 2:
By removing the current-spreading layer, the patent reduces the total semiconductor layer thickness, thereby decreasing light absorption loss while maintaining adequate light emission through the optimized remaining layers.
3Area of moving object
If the μLED chip size is minimized for high resolution, then the display pixel density is improved, but the electron and hole transmission to side wall increases causing no light emission
Solution Approach 1:
The removal of the current-spreading layer eliminates the mechanism that causes carriers to spread laterally to side walls. This extraction is particularly beneficial for miniaturized chips where side wall effects are more pronounced, enabling high-resolution displays without sacrificing light emission efficiency.
Solution Approach 2:
The patent adjusts the thickness parameters of the p-type and n-type layers relative to the reduced chip dimensions. The controlled thickness ratio ensures that carriers are confined within the active region even in miniaturized chips, preventing side wall transmission and maintaining reliable light emission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves light-emitting efficiency by minimizing electron and hole combination with side wall defects, resulting in better light-emitting performance and slimness, suitable for high-resolution displays with reduced power consumption.
Implementation Method 1
a light-emitting layer (120) disposed between the p-type semiconductor layer (110) and the n-type semiconductor layer (130)
Data Source
AI summary
A light-emitting diode chip including a p-type semiconductor layer, a light-emitting layer and an n-type semiconductor layer is provided. The light-emitting layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer. A ratio of a sum of thicknesses of all semiconductor layers of the light-emitting diode chip over a maximum width of the light-emitting diode chip ranges from 0.02 to 1.5. A ratio of a sum of thicknesses of all semiconductor layers located in a side of the light-emitting layer toward the p-type semiconductor layer over the sum of thicknesses of all semiconductor layers of the light-emitting diode chip ranges from 0.05 to 0.2.