Micro-LED Chiplets Wafer-Level Testing and Transfer
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Solution Overview
Problem
Existing display technologies face challenges in reducing the cost and increasing the efficiency of micro-LED displays, particularly in fabricating dense arrays of micro-LEDs on wafers and transferring them to displays while maintaining brightness and efficiency.
Innovation Solution
The use of micro-LED chiplets fabricated in dense arrays on wafers, with local and wafer-level interconnects, allows for the creation of sparse arrays in displays, reducing costs and increasing efficiency by enabling the use of side-contacts and etching trenches for singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If micro-LEDs are fabricated as dense arrays on wafers, then manufacturing efficiency and cost are improved, but the complexity of transferring them to display substrates increases
Solution Approach 1:
The wafer is divided into multiple smaller chiplets through singulation processes. This segmentation allows the large wafer to be handled and transferred in manageable portions, reducing the complexity of transferring dense arrays while maintaining manufacturing efficiency benefits of wafer-level fabrication.
Solution Approach 2:
The patent introduces intermediate structures such as carrier substrates and adhesive layers that facilitate the transfer process. These intermediaries simplify the transfer of micro-LED chiplets from the wafer to the display substrate, making the complex transfer operation more manageable and reliable.
2Illumination intensity
If micro-LEDs are arranged on larger pixel pitches with space between them, then display brightness and efficiency are improved, but the density of micro-LEDs per unit area decreases
Solution Approach 1:
The display is divided into modular chiplets, each containing multiple micro-LEDs. This segmentation allows the micro-LEDs to be densely packed on the wafer during fabrication, then arranged with larger spacing on the display substrate, achieving both high density during manufacturing and optimized spacing for brightness during operation.
Solution Approach 2:
The patent transitions from a two-dimensional dense array on the wafer to a three-dimensional arrangement on the display substrate. By utilizing vertical stacking and depth information, the system achieves high micro-LED density during fabrication while presenting optimized spacing and brightness characteristics on the final display.
3Manufacturing precision
If red, green, and blue color chiplets are transferred separately to the display substrate, then color precision is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
Multiple color chiplets (red, green, and blue) are combined into single integrated pixel chiplets that contain all necessary color elements. This merging reduces the number of separate transfer operations required while maintaining color precision, as all color components are pre-assembled and tested as a unit before transfer to the display substrate.
Solution Approach 2:
The patent performs preliminary assembly and testing of multi-color chiplets on the wafer before transfer to the display substrate. This preliminary action ensures color precision is achieved during fabrication while simplifying the subsequent transfer process, as the complete color array is transferred as a single unit rather than requiring separate transfers for each color.
Data Source
AI summary
Chiplets containing micro-LEDs are designed with two sets of interconnects. One set connects the cathode and anode terminals on the micro-LEDs to contacts for the chiplet. These contacts may then be connected to circuitry outside the chiplet. The other set connects micro-LED terminals to test pads on the wafer when the chiplets are still in wafer form. Multiple chiplets are connected to individual test pads. The micro-LEDs may be fabricated as an array on the wafer, with the test pads arranged around the periphery of the array. As a result, automated test equipment may probe the test pads to test the chiplets while they are still in wafer form.