Micro LED Display Array Layout Without Edge Etching Loss
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Solution Overview
Problem
Conventional micro LED manufacturing processes face challenges in reducing die size due to light emitting efficiency deterioration at the edge and complex, costly manufacturing processes, particularly in creating light emitting platforms and providing electrodes.
Innovation Solution
A display array design featuring a semiconductor stacked layer with a light emitting material layer extending along a reference plane, an insulating layer with openings for electrode pads, and a driving backplane, allowing for electrical isolation of light emitting regions and simplifying the manufacturing process by eliminating the need for edge etching and patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the die size is reduced to nanometer scale, then the device can achieve miniature size, but the light emitting efficiency deteriorates due to edge effects
Solution Approach 1:
The patent divides the semiconductor layer into multiple independent light emitting regions separated by insulating layers. Each region is electrically isolated and can be independently controlled, allowing the overall structure to achieve miniature size while maintaining high light emitting efficiency in each segment without edge effects dominating the performance
Solution Approach 2:
The patent transitions from a conventional planar die structure to a stacked three-dimensional structure with multiple semiconductor layers arranged vertically. This dimensional change allows light emitting regions to be distributed in the vertical direction, reducing the horizontal footprint and achieving miniature size while preserving light emitting efficiency through proper electrical isolation
2Manufacturing precision
If conventional manufacturing processes are used for micro LED arrays, then light emitting platforms can be created, but the manufacturing process becomes complicated and costly
Solution Approach 1:
The patent combines multiple manufacturing steps into a more integrated process. The insulating layers are formed to simultaneously define light emitting regions, provide electrical isolation, and serve as structural support, eliminating the need for separate edge etching and patterning steps that complicate conventional processes
Solution Approach 2:
The patent extracts and eliminates the problematic edge etching and complex patterning steps from the manufacturing process. By forming insulating layers that naturally define the light emitting regions, the process removes the need for additional precision-critical steps, thereby reducing manufacturing complexity and cost while maintaining the required precision
Data Source
AI summary
A display array including a semiconductor stacked layer, an insulating layer, a plurality of electrode pads, and a driving backplane is provided. The semiconductor stacked layer has a plurality of light emitting regions arranged along a reference plane. The insulating layer is disposed to an outer surface of the semiconductor stacked layer and contacts the semiconductor stacked layer. The insulating layer has a plurality of openings respectively corresponding to the plurality of light emitting regions. The electrode pads are disposed to the insulating layer and are respectively electrically connect the plurality of light emitting regions through the plurality of openings. The driving backplane is disposed to the semiconductor stacked layer and electrically connected to the plurality of electrode pads, wherein a light emitting material layer of the semiconductor stacked layer has consistency along an extension direction of the reference plane.