Co-Planar Micro-LED Electrodes for Fluidic Assembly
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Solution Overview
Problem
The challenge in micro-LED display technology is achieving high yield and reliability in fluidic assembly processes due to non-co-planar electrode interfaces, which lead to incomplete electrical connections and high series resistance, particularly in high-resolution displays requiring precise planarity and adaptability in brightness and resolution.
Innovation Solution
The development of micro-light emitting diode (LED) structures with a diameter between 10 and 150 μm, featuring an electrode structure compatible with conventional MOCVD growth technology, where the electrodes are fabricated to be electrically and physically bonded to display substrates, allowing for adjustable pixel brightness without altering the micro-LED structure, ensuring co-planar substrate interface surfaces through precise etching and insulator deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional LED fabrication processes are used, then manufacturing cost and complexity are reduced, but electrode interface planarity deteriorates leading to incomplete electrical connections
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer of dielectric material over the LED stack before creating contact holes. This pre-planarization step ensures that the electrode interfaces are co-planar before the fluidic assembly process, preventing incomplete electrical connections while maintaining compatibility with conventional LED fabrication processes. The dielectric layer is deposited to a thickness that compensates for surface irregularities in the underlying LED structure.
Solution Approach 2:
The patent introduces a dielectric material as an intermediary layer between the LED stack and the electrode contacts. This intermediary dielectric layer serves multiple functions: it provides mechanical support, ensures electrical isolation, and most importantly, creates a planar surface for electrode interfacing. The dielectric material fills in valleys and covers peaks in the LED surface topology, acting as a mediator that transforms the non-planar LED surface into a planar electrode interface.
2Reliability
If electrode planarity is improved through additional processing steps, then electrical connection reliability is enhanced, but device complexity and manufacturing cost increase
Solution Approach 1:
The dielectric material layer serves multiple functions simultaneously: it provides electrical insulation between conductive elements, mechanical planarization of the surface, structural support during handling, and a platform for subsequent electrode deposition. By combining these functions into a single layer, the patent avoids the need for multiple separate processing steps that would increase device complexity and manufacturing cost.
Solution Approach 2:
The patent controls the thickness and material properties of the dielectric layer to optimize its planarization effect. By adjusting the dielectric layer thickness parameter to be sufficient to cover surface irregularities but not excessively thick, the patent achieves co-planar electrode interfaces without adding unnecessary complexity. The dielectric material's physical and chemical parameters are selected to ensure compatibility with subsequent processing steps.
3Productivity
If micro-LED structure is modified to achieve co-planar electrodes, then fluidic assembly yield is improved, but adaptability in brightness and resolution is reduced
Solution Approach 1:
The patent segments the electrode formation process from the LED structure fabrication process. By using the dielectric planarization layer as an independent intermediate structure, the LED active region can be optimized for brightness and resolution while the electrode interface is separately optimized for co-planarity. This segmentation allows independent optimization of both the light-emitting properties and the electrical connection properties without compromising either.
Solution Approach 2:
The dielectric layer acts as an intermediary that decouples the LED structure design from the electrode interface design. This intermediary layer allows the micro-LED structure to maintain its original geometry optimized for light emission, while the dielectric layer provides the necessary planarization for high-yield fluidic assembly. The intermediary thus preserves the adaptability of the LED structure for different brightness and resolution requirements.
Data Source
AI summary
Planar surface mount (SM) micro light emitting diodes (μLEDs) are presented. The fabrication method provides a MOCVD LED structure with a stack including a first doped semiconductor in a first plane, a MQW layer overlying the first doped semiconductor in a second plane, and a second doped semiconductor overlying the MQW layer in a third plane. An electrical insulator is conformally deposited over the etched stack in a fourth plane, and etched to expose the second doped semiconductor, creating a first via. Etching exposes the first doped semiconductor, creating a second via. A first electrode is connected to the second doped semiconductor through the first via, and has a substrate interface surface in a fifth plane with an average planarity tolerance of less than 10 nanometers. A second electrode is connected to the first doped semiconductor through the second via, and has a substrate interface surface in the fifth plane.