Micro-LED Growth on Hetero-Interface Without Etch Sidewall Damage
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Solution Overview
Problem
Current methods for fabricating III-nitride micro-LEDs face issues such as surface and sidewall damage from dry etching, leading to decreased peak external quantum efficiency, significant material waste, and limitations in achieving ultra-high response speeds for future display and VLC applications.
Innovation Solution
A method involving the formation of a semiconductor layer with a dielectric mask layer having holes, allowing for upward growth of LED structures within these holes, which reduces sidewall damage and enables efficient material use while enabling ultra-fast electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dry etching processes are used to define μLED mesas, then device fabrication can be achieved, but surface and sidewall damage is introduced which significantly enhances the non-radiative recombination rate and decreases peak external quantum efficiency
Solution Approach 1:
A dielectric mask layer is introduced as an intermediary between the semiconductor layer and the etching process. The mask layer is patterned with holes that expose only the desired mesa areas, allowing etching to proceed without direct plasma contact to the sidewalls, thereby preventing damage while maintaining fabrication capability
Solution Approach 2:
The semiconductor layer is segmented into discrete mesa regions separated by dielectric material. This segmentation is achieved by patterning the dielectric mask layer with an array of holes, creating isolated growth regions that avoid the harmful effects of dry etching on continuous surfaces
2Length of moving object
If the device dimension is reduced to micrometer scale, then high resolution and high brightness display applications are enabled, but the surface area to bulk volume ratio increases which exacerbates surface recombination and sidewall damage effects
Solution Approach 1:
A thin dielectric mask layer is deposited over the semiconductor layer, creating a protective film that defines the mesa regions. This thin film approach allows precise dimensional control at micrometer scale while protecting the semiconductor surfaces from damage during fabrication
Solution Approach 2:
The problem is solved by adding a vertical dimension - the dielectric mask layer is deposited in the vertical direction over the semiconductor layer, creating a three-dimensional structure where the mask thickness and hole geometry control the final mesa dimensions without requiring aggressive lateral etching
3Productivity
If standard photolithography and dry etching are used for μLED fabrication, then device arrays can be produced, but significant material waste occurs as huge areas of the epiwafer must be etched away
Solution Approach 1:
Instead of etching away large areas to leave small devices, the approach is inverted: the dielectric mask is deposited completely over the wafer, then holes are formed only where devices should be, and etching is restricted to these hole regions. This leaves the majority of the epiwafer material intact for potential reuse or other applications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the internal quantum efficiency of micro-LEDs, reduces material waste, and facilitates faster growth rates, addressing the limitations of conventional fabrication techniques.
Implementation Method 1
growing an LED structure in each of the holes
Data Source
AI summary
An array of semiconductor structures is grown on a hetero-interface barrier layer by forming successive semiconductor layers within holes formed through a dielectric layer deposited above the hetero-interface barrier layer. The hetero-interface forms a two dimensional charge carrier gas. Each semiconductor structure is grown within one of the holes and includes at least one LED active layer between an n-type semiconductor layer and a p-type semiconductor layer. The bottom one of the two semiconductor layers has the same conductivity type as the barrier layer on which it is formed. The hetero-interface is defined between the barrier layer and a buffer layer. The barrier layer and buffer layer can be formed from GaN, AlGaN, and/or InGaN of varying concentrations. The two dimensional charge carrier gas can be a 2D electron gas or a 2D hole gas.