Micro-LED Displays on Patterned Templates
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Solution Overview
Problem
Micro-LEDs face efficiency losses due to defects at the etch sidewalls, leading to non-radiative carrier recombination and leakage currents, which are difficult to address with existing passivation methods, especially as device dimensions decrease, and the high cost and complexity of pick-and-place methods for fabricating large display panels.
Innovation Solution
The use of patterned substrates with epitaxial layers and sloped sidewalls, where the p-layer is thicker on the flat regions and thinner on the sloped sidewalls, reducing parasitic hole leakage and enhancing carrier confinement, along with the elimination of pick-and-place methods by forming LEDs at the wafer level and bonding them to a backplane before or after etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If LEDs are fabricated using conventional planar structures with uniform epitaxial layers, then the fabrication process is simple, but sidewall defects cause non-radiative recombination and leakage currents that reduce efficiency
Solution Approach 1:
The patent applies local quality by creating non-uniform epitaxial layers with different thicknesses in different spatial locations. Specifically, the p-layer and n-layer are designed to be thicker at mesa regions and thinner at sidewall regions, allowing the structure to have optimized properties at each location: thicker layers at mesas provide good electrical contact and carrier injection, while thinner layers at sidewalls reduce defect density and minimize non-radiative recombination losses.
2Productivity
If device dimensions are reduced to create high-density displays, then display density increases, but sidewall defect impact increases leading to more leakage currents
Solution Approach 1:
The patent applies parameter changes by systematically varying the thickness parameters of the epitaxial layers based on location. The p-layer thickness is changed from a uniform value to a position-dependent value that is thicker at mesas and thinner at sidewalls. Similarly, the n-layer thickness is optimized independently at different locations. This parameter optimization reduces the impact of sidewall defects while maintaining high device density.
3Manufacturing precision
If pick-and-place methods are used to fabricate large display panels, then individual LED placement is precise, but fabrication cost and complexity increase significantly
Solution Approach 1:
The patent applies merging by integrating multiple fabrication steps into a unified wafer-level process. Instead of separately fabricating individual LEDs and then placing them using pick-and-place methods, the invention combines LED formation, epitaxial layer growth, and array patterning into a single monolithic wafer fabrication process. This merging eliminates the need for complex pick-and-place operations while maintaining manufacturing precision through controlled epitaxial growth and wafer-level patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces sidewall recombination, increases electrical resistance, and decreases fabrication costs, enabling efficient, flexible, and cost-effective production of high-density display panels with uniform emission and reduced color shift, suitable for large area displays and compact form factors.
Implementation Method 1
A first flat region at a first height from a reference point (e.g., a base of an LED, a contact, a backplane, etc), including a plurality of epitaxial layers such as a first n-layer, a first p-layer, and a first active layer
Data Source
AI summary
Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height, including a plurality of epitaxial layers such as a first n-layer, a first p-layer, and a first active layer. A second flat region at a second height and parallel to the first flat region includes at least a second n-layer. Sloped sidewalls connect the first flat region and the second flat region and include at least a third n-layer. The p-layer of the first flat region is thicker that at least a portion of the third region. A p-contact is formed on the first p-layer and an n-contact is formed on the second n-layer.