Micro LED Tapered Semiconductor Layer Sidewall Carrier Management
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Solution Overview
Problem
Micro light-emitting diodes (LEDs) face efficiency droop effects and sidewall damage during etching processes, leading to decreased external quantum efficiency, especially when the size is less than 50 micrometers, due to increased carrier flow through the sidewalls.
Innovation Solution
The design includes a first-type semiconductor layer with a first portion and a second portion connected to each other, where the bottom area of the first portion is smaller than the top area of the second portion, and a conductive layer is placed between the electrode and the first portion, with an orthographic projection area covering at least 90% of the first portion, reducing the thickness of the peripheral edge and increasing thin film resistance, thereby reducing carrier flow to the sidewalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the size of micro light-emitting diode is reduced to less than 50 micrometers, then the device achieves miniaturization and higher pixel density, but the proportion of carriers flowing through the sidewall increases, resulting in substantial decrease in external quantum efficiency
Solution Approach 1:
The patent applies local quality by creating a tapered first-type semiconductor layer where the thickness varies spatially - thinner at the peripheral edge and thicker at the center. This non-uniform thickness distribution locally modifies the carrier flow characteristics, directing carriers away from the sidewall region toward the center where the light-emitting layer is most effective, thereby resolving the efficiency loss in miniaturized devices
Solution Approach 2:
The patent introduces a dimensional change by transitioning from a uniform thickness structure to a tapered thickness profile in the first-type semiconductor layer. This dimensional variation along the vertical axis creates a gradient that influences carrier transport paths, effectively managing carrier distribution in miniaturized devices without further reducing the lateral dimensions
2Ease of manufacture
If etching process is used for mesa and isolation procedures, then the device structure is formed, but the sidewalls of the micro light-emitting diode are damaged
Solution Approach 1:
The patent applies preliminary action by pre-forming the tapered thickness profile in the first-type semiconductor layer before the etching process. This pre-structured geometry ensures that when etching is performed for mesa and isolation, the sidewalls are already optimized to be thinner at the edges, reducing the impact of etching damage and preventing excessive carrier flow to damaged regions
Data Source
AI summary
A micro light-emitting device includes an epitaxial structure, a first electrode, a second electrode and a conductive layer. The epitaxial structure includes a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer. The first-type semiconductor layer includes a first portion and a second portion. A bottom area of the first portion is smaller than a top area of the second portion. A thickness of the second portion is greater than 10% of a thickness of the first-type semiconductor layer. The first electrode is disposed on the epitaxial structure and located on the first portion of the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure. The conductive layer is disposed between the first electrode and the first portion, wherein an orthographic projection area of the conductive layer on the first portion is greater than or equal to 90% of an area of the first portion.