Micro-LED Tiling Panel Layout for EMI Cancellation and Timing Stability
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Solution Overview
Problem
Micro-LED display devices face challenges in designing a tiling display apparatus with pseudo signal lines for EMI stabilization due to spatial pattern design limitations of high voltage gate signal lines, panel thickness affecting voltage electrode and ground plane spacing, and timing dispersion leading to screen discontinuity.
Innovation Solution
A micro-LED display device and tiling display apparatus are designed with a lower substrate pattern and circuit to cancel EMI from the gate clock signal, using a conductive adhesive between substrates for stable voltage supply and phase compensation signals to prevent timing dispersion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a pseudo signal line is added to the upper substrate for EMI stabilization, then EMI reduction is improved, but the spatial pattern design becomes more complex and difficult to implement
Solution Approach 1:
The patent moves the pseudo signal line from the upper substrate to the lower substrate, utilizing the vertical dimension (substrate layering) to resolve the spatial constraint. This allows the EMI cancellation structure to be implemented without complicating the upper substrate's pattern design, as the pseudo signal line is now routed on a different layer beneath the gate clock signal line.
Solution Approach 2:
The patent divides the EMI cancellation function into separate components: the gate clock signal line remains on the upper substrate while the pseudo signal line is implemented on the lower substrate. This segmentation allows each substrate to be designed independently with optimized patterns, reducing the overall design complexity while maintaining EMI reduction effectiveness.
2Object-affected harmful factors
If the spacing between voltage electrode and ground plane is reduced to stabilize panel common noise, then noise stabilization is improved, but panel thickness becomes a limiting factor
Solution Approach 1:
The patent utilizes the vertical stacking dimension by placing the ground plane on the lower substrate beneath the voltage electrode on the upper substrate. This three-dimensional arrangement allows for effective noise stabilization without being constrained by lateral spacing, as the distance between voltage electrode and ground plane is determined by the substrate thickness rather than lateral dimensions.
3Object-affected harmful factors
If timing dispersion is applied to avoid noise overlapping gate clock signal, then noise interference is reduced, but screen discontinuity occurs
Solution Approach 1:
The patent implements preliminary anti-action by introducing a pseudo signal line that generates an opposing electromagnetic field to cancel the gate clock signal noise before it can cause interference. The pseudo signal is timed and phased to preemptively counteract the noise, preventing both overlapping and screen discontinuity by maintaining signal integrity throughout the display panel.
Data Source
AI summary
Disclosed is a display apparatus including a first panel, a second panel, and a control circuit configured to output a reference gate signal to the first panel and to output a timing-delayed gate clock signal to the second panel. At least one of the panels includes an upper substrate having a micro-LED mounted thereon and a lower substrate connected to the upper substrate via routing.