Micro LED Verification Substrate for Rapid Defect Filtering

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Solution Overview

Problem

Current methods for verifying micro light-emitting diode (LED) chips face challenges in balancing speed and accuracy, as mass transfer is fast but lacks defect filtering, while individual transfer is slow and impractical for large quantities.

Innovation Solution

A micro LED verification substrate with specific structural features and a method involving wafer-bonding, power application, and selective removal of defective chips, followed by stamp transfer and individual chip replacement to achieve rapid verification and high quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If mass transfer using a stamp is used, then transfer speed is high, but defective chips cannot be distinguished and transferred

Engineering Contradiction:
Improvetransfer speedVSAvoiddefect filtering capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The transfer process is segmented into two distinct stages: first, mass transfer of all chips using a stamp to achieve high speed; second, individual transfer of only defective chips for replacement. This segmentation allows the system to benefit from both high-speed mass transfer and accurate defect filtering.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Verification of chip functionality is performed before the final transfer process. By pre-identifying defective chips through electrical testing on the wafer, the system can plan the replacement strategy in advance, ensuring that only necessary individual transfers are performed after mass transfer.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If individual transfer of chips is used, then defective chips can be filtered accurately, but transfer speed is too slow for practical application

Engineering Contradiction:
Improvedefect filtering capabilityVSAvoidtransfer speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

Instead of performing individual transfer on all chips, the system applies individual transfer only to the small subset of defective chips identified during verification. The majority of chips are transferred efficiently using mass transfer, thus achieving high overall speed while maintaining accurate defect filtering where needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The chip population is segmented into two groups: functional chips transferred via high-speed mass transfer, and defective chips requiring individual transfer. This segmentation minimizes the number of slow individual operations while ensuring complete defect filtering.

Inventive Principle:
Principle #1Segmentation

3Productivity

If all chips are transferred regardless of defect status, then transfer process is simple and fast, but additional process steps are required to remove defective chips later

Engineering Contradiction:
Improvetransfer efficiencyVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The verification process provides feedback on chip functionality before transfer. This feedback information is used to generate a transfer map that guides the subsequent replacement process, allowing the system to optimize the transfer strategy based on actual chip status rather than treating all chips uniformly.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

By performing verification and creating a transfer plan before the actual transfer, the system prepares the optimal transfer strategy in advance. This preliminary action reduces the complexity of post-transfer defect removal by pre-identifying which chips need individual handling.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables rapid verification and transfer of micro LEDs with improved speed and quality by distinguishing and removing defective chips, combining the advantages of mass and individual transfer methods.

Implementation Method 1

The step (b) may include removing the lowermost substrate by laser lift-off (LLQ), wherein the lowermost substrate is a sapphire substrate.

Methodology Applied
Scientific EffectLaser lift-off: Laser Ablation

Implementation Method 2

applying power to a first contact and a second contact of the micro LED verification substrate, and (d) removing LED chips that do not emit light

Methodology Applied
Scientific EffectLight emission from LED: Light Emitting Diode

Implementation Method 3

applying power to a first contact and a second contact of the micro LED verification substrate, and (d) removing LED chips that do not emit light

Methodology Applied
Scientific EffectElectroluminescence: Electroluminescence

Implementation Method 4

placing a first photoresist having a first shape on an upper side of the first passivation layer, (d) depositing a second contact on an upper side of the first photoresist and on the upper side of the first passivation layer that is not covered by the first photoresist

Methodology Applied
Scientific EffectPhotoresist protection: Photography

Data Source

PatentUS11728225B2Micro LED verification substrate, manufacturing method therefor, and micro LED verification method using same
Publication Date: 2023.08.15 RES COOPERATION FOUND OF YEUNGNAM UNIV
  • US11728225B2 patent drawing
  • US11728225B2 patent drawing
  • US11728225B2 patent drawing

AI summary

Disclosed in the present specification are an apparatus and a method capable of quickly verifying a plurality of micro LEDs. An LED verification substrate according to the present specification is a micro LED verification substrate having a plurality of verification chips, wherein each verification chip can comprise: a first contact deposited on the upper side of a lower substrate; a first passivation layer deposited on the upper side of the first contact; a second contact deposited on the upper side of the first passivation layer; a second passivation layer deposited on the upper side of the second contact; a first bump electrically connected to the first contact and protruding above the upper surface of the second passivation layer; and a second bump electrically connected to the second contact and protruding above the upper surface of the second passivation layer.