Micro Networks-On-Chip for Faster Circuit Configuration
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Solution Overview
Problem
Configuring configurable integrated circuits through configuration networks-on-chip (CNOCs) requires substantial runtime due to limited bandwidth, which hampers efficient configuration and emulation operations.
Innovation Solution
Employing micro networks-on-chip (NOC) to decouple from response buffer circuits and couple with local configuration managers (LCMs) for faster configuration and emulation operations, utilizing high-bandwidth paths and double-pumping interfaces to maintain data bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If configuration networks-on-chip (CNOCs) are used for configuring integrated circuits, then configuration data can be transmitted to logic circuits, but the runtime for configuration and emulation operations becomes substantial due to limited bandwidth
Solution Approach 1:
The patent divides the configuration network into multiple micro NOCs that operate in parallel across different regions of the integrated circuit. Each micro NOC handles configuration data for a specific region, allowing simultaneous configuration operations across multiple regions and reducing overall configuration runtime by an order of magnitude.
Solution Approach 2:
The patent introduces a spatial dimension to data transmission by routing configuration data through multiple parallel paths across different regions of the circuit. This dimensional expansion from a single sequential path to multiple parallel paths enables concurrent configuration operations and significantly reduces configuration time.
2Loss of time
If micro networks-on-chip (NOCs) are used to transmit configuration data, then configuration runtime is reduced, but the network complexity increases due to decoupling from response buffer circuits
Solution Approach 1:
The patent extracts the micro NOCs from the traditional response buffer circuit structure and couples them directly with local configuration managers. This extraction simplifies the overall system architecture by removing unnecessary intermediate components while reducing configuration runtime through more direct data paths.
Solution Approach 2:
The patent introduces local configuration managers as intermediary components between the micro NOCs and the logic circuits. These managers coordinate configuration data transmission and simplify the interaction between the micro NOCs and the target logic circuits, reducing the overall system complexity despite the increased number of components.
3Speed
If high-bandwidth paths are used in micro NOCs, then data transmission speed increases, but the device complexity increases due to additional interfaces and routing
Solution Approach 1:
The patent segments the high-bandwidth data transmission paths into multiple dedicated micro NOCs, each handling specific data streams. This segmentation allows each micro NOC to maintain high bandwidth with simplified routing structures, as each path is dedicated to specific configuration or emulation data rather than requiring complex multiplexing.
Solution Approach 2:
The patent implements local configuration managers that are optimized for their specific regions, with dedicated interfaces and routing structures tailored to local needs. This local optimization reduces the complexity of each individual interface while maintaining high overall bandwidth through parallel operations across multiple regions.
Data Source
AI summary
An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.