Micro NOC Interconnects for FPGA Memory Traffic

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Solution Overview

Problem

Integrated circuits, such as FPGAs, face inefficiencies in communication between network-on-chip (NOC) and memory blocks due to the use of fabric resources and soft logic, which limits their ability to perform other functions like data processing.

Innovation Solution

Implementing micro networks-on-chip (micro NOCs) as hardened connections within the integrated circuit, using a response buffer to intercept and route data between NOCs and memory blocks more efficiently, thereby reducing latency and increasing throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fabric resources and soft logic are used to enable communication between NOC and memory blocks, then communication functionality is achieved, but integrated circuit efficiency is reduced due to resource unavailability for other functions

Engineering Contradiction:

Improvecommunication functionalityVSAvoidintegrated circuit efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the communication path by introducing dedicated micro NOC interconnect structures that separate memory-to-NOC traffic from the general-purpose fabric resources. This segmentation allows fabric resources to be freed for other functions while micro NOC handles memory communication specifically.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces micro NOC as an intermediary layer between memory blocks and the main NOC. This intermediary structure provides dedicated communication paths that reduce reliance on fabric resources and soft logic, thereby improving overall circuit efficiency while maintaining communication functionality.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If fabric resources are used for data transport between NOC and memory blocks, then data communication is enabled, but resource availability for data processing functions is reduced

Engineering Contradiction:

Improvedata communication capabilityVSAvoidresource availability for data processing

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent divides the interconnect resources into dedicated micro NOC structures for memory access and general-purpose fabric resources for data processing. This segmentation ensures that fabric resources remain available for diverse data processing functions while micro NOC handles memory communication tasks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The micro NOC structures provide self-service for memory communication needs, freeing up fabric resources to serve data processing functions. The dedicated interconnect structures independently handle memory traffic without consuming general-purpose fabric resources.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20220221986A1Fabric memory network-on-chip

Publication Date: 2022.07.14 ALTERA CORP

AI summary

An integrated circuit device includes a programmable fabric that has a plurality of memory blocks. The integrated circuit device also includes a network-on-chip (NOC) located on a shoreline of the programmable fabric and at least one micro NOC formed with hardened resources in the programmable fabric. The at least one micro NOC is communicatively coupled to the NOC and to at least one memory block of the plurality of memory blocks. Additionally, the at least one micro NOC is configurable to route data between the NOC and the at least one memory block.