Micro OLED Pixel Circuit Layout With Shared Gate Vias for Ultra-High PPI
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Solution Overview
Problem
Existing micro OLED display technologies face challenges in achieving ultra-high pixels per inch (PPI) due to limitations in design and layout of pixel driving circuits, which hinder the development of high-resolution displays.
Innovation Solution
A display substrate design with integrated gate electrodes and shared gate via holes, along with a specific layout of transistors and signal lines, allows for ultra-high PPI by maximizing the packing density of sub-pixels, utilizing a 3T1C pixel driving circuit and optimizing the arrangement of active layers and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel driving circuit layout is optimized to increase packing density, then pixels per inch (PPI) is improved, but the design complexity of the circuit layout increases
Solution Approach 1:
The pixel driving circuit is segmented into multiple functional blocks (first transistor for data input, second transistor for light emission control, third transistor for reference voltage input, and storage capacitor). This segmentation allows each component to be independently optimized and positioned to maximize packing density while maintaining clear design rules for manufacturing.
Solution Approach 2:
Adjacent gate electrodes are merged to form shared gate structures that serve multiple transistors. This merging reduces the total number of separate gate electrodes and via holes required, simplifying the overall layout design while increasing the effective packing density of functional elements within the pixel area.
2Manufacturing precision
If more transistors and signal lines are integrated into each pixel, then display resolution is improved, but the area occupied by each sub-pixel increases
Solution Approach 1:
The circuit elements are arranged in a compact planar configuration that efficiently utilizes two-dimensional space. The gate electrodes, active layers, and via holes are positioned in overlapping and adjacent relationships that minimize the footprint of each sub-pixel while accommodating all necessary circuit components for high-resolution display.
Solution Approach 2:
The circuit components are nested within each other in a hierarchical manner, with gate electrodes positioned over active layers, and via holes connecting different conductive layers. This nested arrangement allows maximum integration of functional elements within the minimal sub-pixel area required for high PPI displays.
3Ease of manufacture
If gate via holes are shared between adjacent transistors, then manufacturing complexity is reduced, but the precision of via hole positioning requirements increases
Solution Approach 1:
The gate via holes serve multiple functions: they connect scan signal lines to gate electrodes of multiple adjacent transistors simultaneously. This multi-functionality reduces the total number of via holes required, simplifying the manufacturing process while the via holes are positioned at standardized locations that can be precisely controlled using existing semiconductor fabrication techniques.
Data Source
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AI summary
A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of subpixels; the subpixels comprise first regions (q1), gap regions (q3), and second regions (q2); the subpixels comprise first transistors (T1), second transistors (T2), and third transistors (T3); the first transistors (T1) comprise first active layers (1) and first gate electrodes (11); the second transistors (T2) comprise second active layers (2) and second gate electrodes (12); the third transistors (T3) comprise third active layers (3) and third gate electrodes (13); the first active layers (1) are provided in the first regions (q1); the second active layers (2) and the third active layers (3) are provided in the second regions (q2); and via holes through which the first gate electrodes (11) and the third gate electrodes (13) are connected to scanning signal lines and via holes through which the second gate electrodes (12) are connected to the first transistors (T1) are all formed in the gap regions (q3).