Micro-operation Cache Predictive Allocation for Power Reduction
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Solution Overview
Problem
Mobile processors face challenges in reducing power consumption without performance penalties, particularly due to thermal limitations and battery life constraints, in the execution of micro-operations within the instruction cycle.
Innovation Solution
A micro-operation cache system using predictive allocation, which includes an instruction fetch unit, decode unit, execution unit, and a branch prediction circuit to identify repeating kernels of instructions, allowing for storage and retrieval of micro-operations without the need for constant instruction decoding, thereby enabling power-saving modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If instructions are constantly decoded from the instruction cache, then performance is maintained, but power consumption increases
Solution Approach 1:
The micro-operation cache stores pre-decoded micro-operations from repeating instruction kernels, so that when these instructions are encountered again, the already-decoded micro-operations can be directly supplied to the execution unit without repeating the decode process, thus saving power while maintaining performance
Solution Approach 2:
Instead of re-decoding instructions from the instruction cache, the system creates and stores copies of decoded micro-operations in the micro-operation cache, which can then be retrieved and executed directly, eliminating redundant decode operations and reducing power consumption
2Temperature
If the instruction decode unit operates continuously, then performance is maintained, but thermal generation increases
Solution Approach 1:
By pre-decoding instruction kernels and storing the resulting micro-operations in the micro-operation cache, the decode unit can be powered down or idle during subsequent executions of the same kernel, reducing thermal generation while maintaining execution performance through cache retrieval
Solution Approach 2:
The system alternates between active decode operations for new instruction kernels and idle/cache-retrieval modes for repeating kernels, creating periodic operation patterns that reduce average thermal generation while maintaining overall performance
3Use of energy by moving object
If the micro-operation cache is populated with repeating kernels, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The micro-operation cache serves multiple functions: it acts as a standard cache for stored micro-operations, enables power-saving modes for repeating kernels, and works in conjunction with the branch prediction circuit to identify and cache repeating instruction patterns, thereby justifying the added complexity through multi-functional benefits
Data Source
AI summary
According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.