Integrated Micro-Peltier Cooling in Silicon-on-Insulator Layers
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Solution Overview
Problem
Conventional cooling methods for integrated circuits (ICs) fail to address localized overheating issues within specific layers or regions of the chip, as they primarily focus on cooling the entire chip rather than targeting hot spots.
Innovation Solution
The implementation of thermoelectric cooling devices, specifically Peltier coolers, are strategically placed over elevated temperature regions within the ICs, using a silicon-on-insulator (SOI) substrate with oxide layers and through-silicon vias to effectively manage temperature control proximate semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional cooling methods are used to cool the entire chip, then the overall chip temperature is reduced, but localized overheating issues in specific layers and regions remain unaddressed
Solution Approach 1:
The cooling system is segmented into multiple independent thermoelectric cooling devices, each targeted at specific elevated temperature regions within the chip. This segmentation allows different zones to be cooled independently according to their specific thermal requirements, rather than applying uniform cooling across the entire chip.
Solution Approach 2:
The patent implements local quality by placing thermoelectric cooling devices at specific locations corresponding to elevated temperature regions identified through functional simulation. Each cooling device is positioned to address the thermal characteristics of its specific region, providing localized temperature control rather than uniform cooling.
2Reliability
If thermoelectric cooling devices are strategically placed over elevated temperature regions, then localized temperature control is improved, but device complexity increases
Solution Approach 1:
The handle wafer serves multiple functions: it provides mechanical support for the chip, acts as a substrate for bonding thermoelectric cooling devices, and facilitates thermal management. This multi-functionality reduces the need for additional separate components, thereby managing complexity while achieving localized cooling.
Solution Approach 2:
The thermoelectric cooling devices are integrated within the existing chip structure by bonding them to the handle wafer beneath the chip. This nesting approach allows the cooling system to be embedded within the chip's architectural layers, minimizing additional space requirements and reducing overall system complexity.
3Manufacturing precision
If functional simulation is used to identify elevated temperature regions, then cooling device placement precision is improved, but manufacturing time increases
Solution Approach 1:
Functional simulation is performed during the design phase to identify elevated temperature regions before actual chip manufacturing and assembly. This preliminary action allows the thermal characteristics to be analyzed and cooling device locations to be determined in advance, enabling precise placement without adding time to the manufacturing process itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for localized and efficient temperature management, enhancing the performance and reliability of ICs by directly addressing hot spots, thereby improving the overall cooling efficiency and reducing thermal stress on critical components.
Implementation Method 1
forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device
Data Source
AI summary
Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.