Micro-processor Circuit for Neural Network Truncation
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Solution Overview
Problem
Conventional processor architectures waste computation resources when executing neural network operations due to large storage requirements and inefficient data processing in SRAM and DRAM, particularly in binary and ternary neural network operations.
Innovation Solution
A micro-processor circuit employing a SIMD architecture with a parameter generation module, compute module, and truncation logic that processes input and weight parameters in parallel to generate sub-output parameters, sum them, and perform truncation to efficiently produce output parameters, thereby optimizing computation resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional processor architecture is used for neural network operation, then storage space is sufficient, but computation resource is wasted
Solution Approach 1:
The processor is divided into multiple SIMD lanes (e.g., 8-bit SIMD lanes) that can process multiple data elements in parallel. Each lane handles specific portions of the neural network computation, enabling simultaneous processing of multiple input data elements with their corresponding weight parameters, thereby improving computation efficiency and reducing resource waste
Solution Approach 2:
The system dynamically adjusts the bit-width parameters of the SIMD lanes to match the precision requirements of different neural network operations. For binary neural networks, 1-bit weight parameters are used; for ternary neural networks, 2-bit weight parameters are used; and for standard neural networks, higher precision parameters are applied. This parameter adaptation optimizes computation resource utilization for different workloads
2Productivity
If conventional processor executes binary/ternary neural network operation, then operation is completed, but computation resource efficiency is low
Solution Approach 1:
The computation is segmented into parallel operations across multiple SIMD lanes, where each lane independently processes specific data elements. This segmentation enables simultaneous execution of multiple multiply-accumulate operations, significantly improving productivity for binary and ternary neural network operations while reducing overall computation resource consumption through parallelization
Solution Approach 2:
The SIMD processor is designed with universal functionality to handle multiple types of neural network operations (binary, ternary, and standard precision) using the same hardware architecture. By configuring the weight parameter bit-width according to the specific operation type, the system achieves multi-functionality without requiring separate specialized hardware for each operation type, thereby improving computation resource efficiency
Data Source
AI summary
A micro-processor circuit and a method of performing neural network operation are provided. The micro-processor circuit is suitable for performing neural network operation. The micro-processor circuit includes a parameter generation module, a compute module and a truncation logic. The parameter generation module receives in parallel a plurality of input parameters and a plurality of weight parameters of the neural network operation. The parameter generation module generates in parallel a plurality of sub-output parameters according to the input parameters and the weight parameters. The compute module receives in parallel the sub-output parameters. The compute module sums the sub-output parameters to generate a summed parameter. The truncation logic receives the summed parameter. The truncation logic performs a truncation operation based on the summed parameter to generate a plurality of output parameters of the neural network operation.