Micro-processor Circuit for Neural Network Operations
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Solution Overview
Problem
Conventional processor architectures waste computation resources when executing neural network operations due to inefficient handling of binary and ternary neural networks, leading to excessive storage and data exchange between memory types.
Innovation Solution
A micro-processor circuit employing a SIMD architecture with a parameter generation module, compute module, and compare logic that processes input and weight parameters in parallel to generate sub-output parameters, sum them, and perform comparisons to produce output parameters, thereby achieving high parallelism and resource efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional processor executes neural network operations using standard architecture, then the operations can be performed, but computation resources are wasted due to inefficient handling of binary and ternary neural networks
Solution Approach 1:
The patent changes the parameter representation by encoding binary weights and inputs into compact 2-bit values (00, 01, 10, 11) representing different multiplication outcomes. This parameter transformation enables the neural network operations to be executed using only addition and comparison operations instead of traditional multiplication, significantly improving computational efficiency and reducing resource consumption for BNN and TNN operations
Solution Approach 2:
The patent segments the neural network computation into distinct functional modules: a parameter generation module that encodes inputs and weights, a compute module that performs parallel additions, and a compare logic module that determines output signs. This segmentation allows each module to be optimized independently, with the compute module using SIMD architecture to process multiple operations simultaneously, thereby improving productivity while reducing overall computational resource waste
2Productivity
If a conventional processor executes neural network operations, then the operations can be completed, but storage space is excessively occupied in SRAM and data exchange between SRAM and DRAM is excessive
Solution Approach 1:
By transforming the computational parameters into compact encoded forms (2-bit representations for binary, 4-bit for ternary), the patent reduces the storage requirements for weights and inputs in SRAM. The encoded parameters require fewer bits to represent the same information, directly reducing the quantity of data stored and exchanged between memory hierarchies while maintaining full operational capability
Solution Approach 2:
The patent extracts and eliminates redundant data storage requirements by using incremental addition instead of full multiplication. Rather than storing and processing complete multiplication results, the system only stores and processes the sign bits and accumulated sum values, removing unnecessary data from the storage system and reducing SRAM occupancy and memory traffic
3Ease of operation
If a processor handles binary and ternary neural network operations with 1-bit or 2-bit weight parameters and 8-bit input data, then the operations can be performed, but computation resources are wasted due to collaboration with 8-bit SIMD lane
Solution Approach 1:
The patent changes the operational parameters by encoding low-precision weights and inputs into compact forms that align with the SIMD lane width. By representing binary values as 2-bit encoded parameters and ternary values as 4-bit encoded parameters, the system enables efficient parallel processing across 8-bit SIMD lanes without wasting computation resources on handling mismatched precision levels
Solution Approach 2:
The patent introduces a new dimensional approach by organizing computations around encoded parameter representations rather than traditional bit-width matching. This allows the system to process multiple low-precision operations simultaneously within the 8-bit SIMD lane by treating the encoded parameters as discrete symbolic units, effectively utilizing the full width of the SIMD lane for parallel processing of multiple neural network operations
Data Source
AI summary
A micro-processor circuit and a method of performing neural network operation are provided. The micro-processor circuit is suitable for performing neural network operation. The micro-processor circuit includes a parameter generation module, a compute module and a compare logic. The parameter generation module receives in parallel a plurality of input parameters and a plurality of weight parameters of the neural network operation. The parameter generation module generates in parallel a plurality of sub-output parameters according to the input parameters and the weight parameters. The compute module receives in parallel the sub-output parameters. The compute module sums the sub-output parameters to generate a summed parameter. The compare logic receives the summed parameter. The compare logic performs a comparison operation based on the summed parameter to generate a plurality of output parameters of the neural network operation.