Micro Semiconductor Stacked Structure for High-Resolution Micro LED Displays

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in reducing the minimum line width and increasing pixel density in micro LED displays due to cost and technical bottlenecks, limiting the advancement of high-resolution displays in a limited area.

Innovation Solution

A micro semiconductor stacked structure is developed, where multiple stacked structures are aligned vertically, each comprising a substrate and micro semiconductor devices connected to a conductive pattern layer, allowing for a decrease in pixel area and increase in pixel density by aligning target regions along the vertical direction, and using active circuits and electronic connecting members for efficient signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If micro LEDs are arranged in a plane to form pixels, then display functionality is achieved, but the pixel area increases and resolution is limited

Engineering Contradiction:
Improvepixel areaVSAvoidresolution
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent transitions from two-dimensional planar arrangement of micro LEDs to three-dimensional stacked structure. Multiple sub-pixel layers (red, green, blue micro LEDs) are stacked vertically along the thickness direction, with each layer containing micro LEDs of a specific color. This vertical stacking enables color synthesis while dramatically reducing the horizontal pixel area, thereby achieving higher resolution displays.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If more pixels are arranged in a limited area to increase resolution, then display density improves, but manufacturing cost and technical difficulty increase

Engineering Contradiction:
ImproveresolutionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent segments the display structure into multiple independent sub-pixel layers, where each layer contains micro LEDs of a specific color (red, green, or blue). Each sub-pixel layer can be manufactured and tested independently, allowing for modular production. This segmentation simplifies the manufacturing process compared to producing complete RGB pixels in a single step, thereby reducing technical difficulty and cost.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a nested structure where multiple sub-pixel layers are stacked one on top of another, with each layer containing micro LEDs of a specific color. The sub-pixels are nested within the vertical space, allowing color synthesis through spatial stacking. This nested arrangement maximizes the use of limited display area while maintaining manageable manufacturing complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Length of moving object

If the minimum line width is reduced to achieve smaller devices, then device size decreases, but manufacturing capability is limited by cost and equipment investment

Engineering Contradiction:
Improvedevice sizeVSAvoidmanufacturing capability
Core Design Contradiction:
Length of moving objectVSEase of manufacture

Solution Approach 1:

Instead of continuing to reduce the horizontal dimensions (line width) of micro LEDs, the patent utilizes the vertical dimension by stacking multiple sub-pixel layers. This approach allows device miniaturization without requiring further reduction in manufacturing line width, thereby avoiding the associated cost and equipment investment barriers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11296061B2Micro semiconductor stacked structure and electronic apparatus having the same
Publication Date: 2022.04.05 LG DISPLAY CO LTD
  • US11296061B2 patent drawing
  • US11296061B2 patent drawing
  • US11296061B2 patent drawing

AI summary

A micro semiconductor stacked structure includes at least two stacked structure array units, wherein one stacked structure array unit is stacked on the other stacked structure array unit. In particular, the stacked structure array unit is stacked on the other stacked structure array unit along a vertical direction. Each stacked structure array unit includes a substrate, a conductive pattern layer disposed on the substrate, and a plurality of micro semiconductor devices disposed on the substrate and electrically connected to the conductive pattern layer.