Micro-sequencer Non-Volatile Memory Channel Control
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Solution Overview
Problem
Conventional non-volatile memory control systems rely on dedicated control logic for each interface protocol, leading to inflexibility and high CPU burden, limiting performance and requiring expensive redesign for new or changed protocols.
Innovation Solution
A system utilizing a general purpose programmable processor in combination with a low-level programmable micro-sequencer for non-volatile memory channel control, allowing clock cycle by clock cycle control and enabling flexibility to handle various non-volatile memory interfaces without pipeline delays, while freeing up the CPU for higher-level tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dedicated control logic is used for each interface protocol, then protocol-specific control functionality is achieved, but device complexity and cost increase with each new protocol requiring redesign
Solution Approach 1:
The patent implements a universal micro-sequencer that can execute different microcode sequences to support multiple non-volatile memory interface protocols (such as NAND, NOR, and other flash interfaces). Instead of having dedicated control logic for each protocol, a single micro-sequencer is programmed with protocol-specific microcode, allowing one hardware structure to perform multiple protocol functions dynamically through software-like programming.
Solution Approach 2:
The patent uses microcode as a programmable representation of control logic. Each interface protocol is implemented by copying the control sequence into microcode form, which can be loaded into the micro-sequencer's control store. This allows protocol implementations to be replicated and modified through programming rather than hardware redesign, enabling flexible support for current and future protocols.
2Adaptability or versatility
If a central processing unit is used for non-volatile memory control, then flexibility in low-level control is achieved, but CPU performance is degraded due to high burden
Solution Approach 1:
The patent divides the control system into two segments: a general-purpose CPU that handles high-level management tasks and a specialized micro-sequencer that handles low-level protocol-specific control. This segmentation allows the CPU to offload time-consuming, protocol-specific microcontrol operations to the micro-sequencer, maintaining system flexibility while preserving CPU performance for higher-level scheduling and management functions.
Solution Approach 2:
The micro-sequencer acts as an intermediary between the CPU and the non-volatile memory interface. It translates high-level CPU commands into detailed protocol-specific control sequences, handling the burden of low-level control operations. This intermediary structure provides the flexibility of programmable control while protecting the CPU from performance degradation.
3Adaptability or versatility
If programmable micro-sequencer is used for low-level control, then adaptability to different protocols is improved, but control structure complexity increases
Solution Approach 1:
The patent implements a nested control structure where the micro-sequencer is integrated within the memory controller, and the control store (memory) is nested within or closely coupled to the micro-sequencer. This nested arrangement allows the programmable micro-sequencer to be embedded within the existing controller architecture, adding protocol adaptability while minimizing the increase in overall structural complexity through compact, integrated design.
Data Source
AI summary
An apparatus includes a device interface, a micro-sequencer, and a programmable sequence memory. The device interface may be configured to process a plurality of read/write operations to/from one or more non-volatile memory devices. The micro-sequencer may be configured to communicate with the device interface. The programmable sequence memory is generally readable by the micro-sequencer. In response to the apparatus receiving a command, (a) the micro-sequencer executes a set of instructions starting at a location in the programmable sequence memory according to the command and (b) the micro-sequencer is enabled to perform at least a portion of the command according to a protocol of the one or more non-volatile memory devices, when the one or more non-volatile memory devices are coupled to the device interface.