Micro Tag Array Way Selection for Cache Power Reduction
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Solution Overview
Problem
Conventional cache access techniques in processors waste energy by energizing and accessing multiple data RAMs during each memory read and write operation, leading to inefficiencies in power consumption.
Innovation Solution
The implementation of a micro tag array that stores base address, offset, and way selection data bits, allowing for early derivation of cache way selection information to enable only the necessary data RAM during cache access, thereby reducing power consumption by disabling unused RAMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple datarams are energized and accessed in parallel during each memory read and write operation, then cache access speed is improved, but power consumption increases
Solution Approach 1:
The micro tag array performs preliminary comparison operations using early stages of the processing pipeline to predict which dataram will contain the required data. This preliminary action enables the system to prepare and enable only the necessary dataram before the actual cache access, avoiding the need to energize all datarams in parallel while maintaining fast access performance.
Solution Approach 2:
The system uses previously accessed way selection information stored in the micro tag array to automatically determine which dataram to access. The micro tag array self-generates the cache dataram enable signal based on historical access patterns, eliminating the need for complex control logic to manage multiple dataram accesses while reducing power consumption.
2Use of energy by moving object
If a micro tag array is implemented to enable only necessary dataram, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The cache structure is segmented into a micro tag array component and the existing tagram/dataram structure. The micro tag array is a separate, simplified component that stores only base address, offset, and way selection data bits. This segmentation allows the complex task of predicting the correct dataram to be handled by a dedicated simple structure, reducing the overall system complexity compared to making the entire cache structure more complex.
Solution Approach 2:
The micro tag array acts as an intermediary between the processing pipeline and the main cache structure. It receives base address and offset information, performs preliminary comparisons, and generates enable signals for the appropriate dataram. This intermediary component simplifies the control logic by handling the prediction function separately, rather than embedding complex control logic within the main cache structure.
Data Source
AI summary
Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal activates only the cache dataram that stores the needed data.