Micro Tag Array Way Selection for Cache Power Reduction
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Solution Overview
Problem
Conventional cache access techniques in processors waste energy by energizing multiple datarams during each memory read and write operation, leading to inefficiencies in power consumption.
Innovation Solution
The implementation of a micro tag array that stores base address data bits, offset data bits, and way selection data bits, allowing for early pipeline stages to derive usable cache way selection information, enabling only the necessary dataram and disabling the tagram during cache access, thereby conserving power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple datarams are energized and accessed in parallel during each memory read and write operation, then cache access speed is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by using early pipeline stages to predict which way (dataram) will be needed before the actual cache access occurs. The micro tag array is populated with address information in advance, allowing the system to determine the required dataram ahead of time and enable only that specific dataram rather than energizing multiple datarams in parallel, thus reducing power consumption while maintaining fast access
2Reliability
If tagrams and datarams are accessed in parallel during each memory operation, then cache operation completeness is improved, but energy waste increases
Solution Approach 1:
The patent applies the taking out principle by extracting only the necessary dataram from the group of datarams that would otherwise be accessed in parallel. The micro tag array enables selective enabling of a single dataram based on predicted address information, removing the need to energize unnecessary datarams and tagrams, thereby eliminating energy waste while still ensuring the correct data is retrieved reliably
3Use of energy by moving object
If a micro tag array is implemented to enable selective dataram access, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the cache structure into a micro tag array component and the existing tagram/dataram structure. The micro tag array is a separate, smaller structure that stores only the essential address information needed for prediction, while the main cache structure remains unchanged. This segmentation allows power reduction through selective access without significantly complicating the overall cache design
Data Source
AI summary
Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register, and a micro tag array. The micro tag array is coupled to the cache and the processor pipeline register. The micro tag array stores base address data bits or base register data bits, offset data bits, a carry bit, and way selection data bits. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal enables only a single dataram of the cache.