Micro TAG Cache Access Using Offset Pointer
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Solution Overview
Problem
Accessing data in large caches is inefficient due to the need for significant power and time in manipulating large addresses, and existing solutions like TLB conversion and microtags are either slow or costly in storage.
Innovation Solution
A data processing apparatus with a set associative cache and a data store that uses a current pointer and region locator to determine cache way access based on offsets, reducing the need for full address storage and minimizing TAG RAM lookups by storing identifiers for consecutive addresses, allowing efficient access within a memory region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a TLB is used to convert virtual address to physical address, then the address conversion can be performed, but the cache access speed is significantly slowed down
Solution Approach 1:
The patent pre-calculates and stores tag values in the data store before they are needed for cache access. By performing the address conversion and tag generation in advance, the actual cache access can proceed without waiting for these computations, thus resolving the speed bottleneck while maintaining accurate address conversion capability
Solution Approach 2:
The patent introduces a data store as an intermediary structure that holds pre-computed tag values and identifier information. This intermediary allows the cache access mechanism to retrieve pre-prepared data without performing real-time address conversion, thereby maintaining both conversion accuracy and access speed
2Productivity
If microtags are used to store cache way information, then the number of TAG RAM lookups is reduced, but the storage requirements increase significantly
Solution Approach 1:
The patent extracts only the essential identifier information from the full address and stores it in the data store alongside tag values. By taking out only the necessary components (identifier and tag) rather than storing complete microtag information, the system reduces storage requirements while still enabling efficient cache way identification through the stored identifier
Solution Approach 2:
The patent implements a partial microtag approach by storing only selected portions of address information (identifier and tag) rather than complete microtag data. This partial action provides sufficient information to reduce TAG RAM lookups while avoiding the excessive storage requirements of full microtag implementation
3Adaptability or versatility
If large addresses are manipulated for cache access, then data in large caches can be accessed, but significant power and time are consumed
Solution Approach 1:
The patent extracts and stores only the relevant tag portion of the address in the data store, rather than manipulating the complete large address during cache access operations. This extraction approach enables access to large caches while significantly reducing the amount of data that needs to be processed, thereby lowering power consumption
Solution Approach 2:
The patent performs address processing and tag extraction in advance, storing the results in the data store. This preliminary action reduces the computational burden during actual cache access operations, enabling support for large cache sizes while minimizing the real-time power consumption associated with address manipulation
Data Source
AI summary
A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache is stored. The plurality of identifiers corresponding to a plurality of values stored in consecutive addresses such that a data store stores identifiers for values stored in a region of said memory. Included is a current pointer store for pointing to a most recently accessed storage location in said data store and circuitry to determine an offset of an address of said cache access request to an immediately preceding cache access request. Lookup circuitry determines if said pointer is pointing to an address within said region and said data processor identifies said cache way from said stored identifier pointed to by said current pointer if it has a valid indicator associated therewith.