Micro-threaded Memory Controller Bandwidth Optimization
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Solution Overview
Problem
Dynamic random access memory (DRAM) core access times have not scaled with memory bandwidth demand, leading to inefficiencies in data transfer and increased power consumption, particularly in applications requiring smaller data objects stored in dispersed memory locations.
Innovation Solution
The implementation of micro-threaded memory operations, where the data transfer capacity over a given time interval is subdivided and allocated to multiple column access transactions, reducing column transaction granularity and increasing effective bandwidth by allowing multiple data objects to be addressed within the same interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If column transaction granularity is increased to maximize data transferred per column access, then peak memory bandwidth increases, but power consumption increases and effectiveness decreases for applications with smaller dispersed data objects
Solution Approach 1:
The patent segments the column access transaction into multiple micro-threaded operations. Instead of transferring a large block of data in a single column access, the data transfer capacity over a given time interval is subdivided and allocated to multiple column access transactions, enabling finer-grained data retrieval that matches the size of smaller dispersed data objects and reduces unnecessary data transfer and power consumption
Solution Approach 2:
The patent introduces dynamic micro-threaded column operations that can adaptively adjust the amount of data transferred per column access based on the specific application requirements. The system dynamically selects between traditional single-threaded mode and micro-threaded mode, optimizing the balance between bandwidth utilization and power consumption for different workload characteristics
2Productivity
If signaling rate is increased to transfer larger amounts of data per column access, then peak memory bandwidth increases, but core access times remain constant and column transaction granularity approaches limits imposed by signal paths within the DRAM itself
Solution Approach 1:
The patent segments the data transfer operation into multiple micro-threaded column accesses, each handling a smaller portion of the total data. This segmentation allows the system to achieve high effective bandwidth without requiring increased signaling rates, thereby avoiding the complexity and physical limits of high-speed signal paths within the DRAM core
Solution Approach 2:
The patent enables continuous utilization of the column access pipeline by overlapping multiple micro-threaded operations. While one micro-thread is being serviced, the system can initiate the next micro-thread, maintaining continuous productive action without requiring peak signaling rates, thus avoiding the associated complexity
3Productivity
If column transaction granularity is reduced to address smaller dispersed data objects, then effective bandwidth for such applications increases, but the amount of data transferred per column access decreases
Solution Approach 1:
The patent segments the overall data transfer requirement into multiple smaller micro-threaded column accesses, each tailored to the size of individual dispersed data objects. This segmentation enables precise matching of transfer granularity to application needs, improving effective bandwidth for small objects while maintaining reasonable data transfer volumes through aggregation across multiple micro-threads
Solution Approach 2:
The patent changes the parameter of column transaction granularity by introducing micro-threaded operations with configurable data transfer sizes. This parameter adjustment allows the system to optimize the balance between transfer efficiency and data object size, transferring smaller amounts per micro-thread but achieving higher effective bandwidth through increased transaction frequency and parallelism
Data Source
AI summary
A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.