Micro TSV Backside Power Rails for Lower IR Droop
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Solution Overview
Problem
Modern semiconductor chips face issues with voltage droop, particularly resistive voltage droop (IR droop), due to increased resistance in power rails and limited vias, leading to reduced yield and performance.
Innovation Solution
Implementing a power connection redundancy system using micro TSVs and backside power rails, which traverse through the silicon substrate to connect with frontside power rails, providing additional conductive paths and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of metal layers is increased to provide more power distribution paths, then power distribution capability is improved, but resistance increases leading to increased voltage droop
Solution Approach 1:
The patent introduces through-silicon vias (TSVs) that traverse the silicon substrate vertically to create backside power rails, adding a third-dimensional power distribution path. This allows power to be delivered from the backside of the chip, creating additional conductive paths that are spatially separated from the frontside metal layers, thereby reducing resistance and voltage droop without increasing the number of frontside metal layers.
Solution Approach 2:
The patent uses micro TSVs as intermediary conductive structures that connect the backside power rails to the frontside power rails. These micro TSVs act as mediators that bridge the two sides of the silicon substrate, providing low-resistance connection paths that reduce the overall resistance in the power distribution network and mitigate voltage droop.
2Adaptability or versatility
If the width of power rails is reduced to accommodate more nodes and signals on the chip, then chip functionality is improved, but resistance of power rails increases
Solution Approach 1:
By routing power rails on the backside of the silicon substrate and using TSVs to connect to the frontside, the patent creates additional power distribution paths in the vertical dimension. This allows the frontside power rails to be made narrower to accommodate more functional nodes while the backside power rails provide compensating conductive paths, maintaining low overall resistance despite reduced frontside rail widths.
3Area of stationary object
If the number of vias on power rails is limited due to on-die area constraints, then chip area efficiency is improved, but manufacturing yield decreases
Solution Approach 1:
The patent moves via formation to the backside of the silicon substrate, where TSVs are formed to connect backside power rails to frontside power rails. This spatial redistribution allows additional via structures to be created without increasing the frontside via count, thereby improving manufacturing yield while maintaining efficient use of frontside die area for functional circuits.
4Object-generated harmful factors
If micro TSVs and backside power rails are implemented to reduce resistance, then voltage droop is reduced, but device complexity increases
Solution Approach 1:
While the patent does increase structural complexity by adding backside power rails and TSVs, it resolves voltage droop by utilizing the vertical dimension for power distribution. The complexity is concentrated in the interconnection structure rather than the functional circuitry, allowing the core logic and memory cells to remain simple while achieving improved power delivery through the three-dimensional TSV-based architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge sharing, improves wafer yield, and reduces voltage droop, thereby maintaining performance and preventing data corruption.
Implementation Method 1
a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer
Implementation Method 2
resistive voltage droop, which is also referred to as the 'IR droop,' that is proportional to the multiplicative product of the current (I) flowing through a metal trace and the resistance (R) of this metal trace
Data Source
AI summary
An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer. The integrated circuit includes, at a second node that receives the power supply reference, a second micro TSV that physically contacts at least one source region. The integrated circuit includes a first power rail that connects the first micro TSV to the second micro TSV. This power rail replaces contacts between the micro TSVs and a second power rail such as the frontside metal zero (M0) layer. Each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.