Micro Well Height Variation for Stronger Semiconductor Signal Detection

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Solution Overview

Problem

Existing semiconductor structures with uniform micro wells face limitations in signal detection efficiency due to insufficient contact area and volume for target substances, leading to weak or inconsistent signal intensity.

Innovation Solution

The development of semiconductor structures with micro wells of varying heights and accommodation volumes, allowing for increased contact surface area and selective signal detection by incorporating transistors connected to dielectric layers with different materials and configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If uniform micro wells are used in semiconductor structures, then manufacturing simplicity is maintained, but signal detection efficiency is insufficient due to limited contact area and volume

Engineering Contradiction:
Improvesignal detection efficiencyVSAvoidmicro well structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating micro wells with varying heights and accommodation volumes within the same semiconductor structure. Different micro wells are designed with different depths to provide optimized contact areas for different target substances, thereby improving signal detection efficiency without requiring complete redesign of the entire structure

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The micro well array is segmented into multiple height levels and accommodation volumes. This segmentation allows different regions of the semiconductor structure to serve different detection purposes, with each segment optimized for specific analyte sizes or concentrations, thus enhancing overall measurement precision

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If micro wells with greater heights and accommodation volumes are used, then contact surface area with testing samples increases and signal intensity is enhanced, but device complexity increases

Engineering Contradiction:
Improvesignal intensityVSAvoidmicro well configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent systematically varies the height and accommodation volume parameters of micro wells to optimize signal intensity. By changing these geometric parameters across different micro wells, the structure achieves enhanced contact surface area with testing samples, leading to stronger detection signals while maintaining a systematic design approach

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If micro wells with different heights are implemented, then differential signal processing and analysis become enabled, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesignal processing capabilityVSAvoidmicro well height control
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent incorporates preliminary action by pre-designing micro wells with specific height variations and accommodation volumes during the manufacturing process. This preliminary structuring enables differential signal processing capabilities to be built into the device architecture itself, allowing versatile analysis of different target substances without requiring post-manufacturing adjustments

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250224365A1Semiconductor structure including micro wells with different heights
Publication Date: 2025.07.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250224365A1 patent drawing
  • US20250224365A1 patent drawing
  • US20250224365A1 patent drawing

AI summary

A semiconductor structure includes a dielectric layer, a first stack and a second stack. The first stack includes a first routing, a first micro well and a first transistor. The first routing formed in the dielectric layer has a first top portion, and a first bottom portion connected to the first transistor. The first micro well extends from an upper surface of the dielectric layer into the first top portion, and has a first height. The second stack includes a second routing, a second micro well, and a second transistor. The second routing formed in the dielectric layer has a second top portion, and a second bottom portion connected to the second transistor. The second micro well extends from the upper surface of the dielectric layer into the second top portion, and has a second height greater than the first height.