Semiconductor Chip Microbump Testing via Intermediary Test Pads
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Solution Overview
Problem
The challenge in testing semiconductor chips with microbumps is that conventional circuit probes are too large for the smaller microbumps, and the use of test pads to overcome this issue occupies valuable surface real-estate on the chip, while also risking damage and corrosion.
Innovation Solution
The implementation of microbumps with test pads that are connected via conductive lines, where the test pads are larger than the microbumps and can be covered with a passivation layer to prevent damage and corrosion, allowing for functional testing without significant surface area loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional circuit probes are used for testing microbumps, then testing can be performed, but the probe size is too large for the smaller microbumps
Solution Approach 1:
The patent introduces test pads as intermediary structures that are larger than microbumps but still smaller than conventional probe sizes. These test pads serve as mediators between the microbumps and the testing probes, allowing standard probes to test microbump functionality without requiring probes to be scaled down to microbump dimensions. The test pads are electrically connected to microbumps through conductive structures, enabling indirect testing.
2Measurement precision
If test pads are used to enable probing, then testing becomes feasible, but valuable surface real-estate on the chip is occupied
Solution Approach 1:
The patent implements test pads with non-uniform size distribution and strategic placement throughout the chip surface. Rather than uniformly distributing large test pads, the design uses locally-optimized pad sizes and positions that minimize overall surface occupation while ensuring adequate testing coverage for different functional regions. This allows testing capability to be achieved with reduced total area consumption.
3Measurement precision
If test pads are exposed on the surface, then testing can be performed, but the pads are at risk of damage and corrosion
Solution Approach 1:
The patent applies passivation layer deposition as a preliminary protective action before the test pads are fully exposed and used. The passivation layer is deposited over the test pads during the manufacturing process, creating a protective barrier that prevents damage and corrosion during subsequent handling, testing, and operation. This preliminary protection ensures pad reliability while maintaining testing functionality.
4Ease of operation
If larger test pads are used to accommodate conventional probes, then testing is easier, but surface area loss increases
Solution Approach 1:
The patent optimizes test pad parameters including size, shape, and spacing to achieve a balance between probe accessibility and area efficiency. By carefully controlling pad dimensions and distributions, the design enables conventional probes to effectively access test structures while minimizing the total surface area consumed by test infrastructure. This parameter optimization allows easier testing without proportionally increasing surface area loss.
Data Source
AI summary
A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.