Microchip Shared Array Repair via Centralized Register

The patent segments the repair information storage into two parts: a compact repair register that stores only the essential repair information (select bits and repair actions) and distributed decode logic modules at each memory array that generate repair signals locally. This segmentation eliminates the need for a single large latch structure and reduces the overall test time by enabling parallel repair operations across multiple memory arrays.

The patent transitions from a centralized repair information storage approach (using many latches) to a distributed approach where repair information is stored in a compact register and distributed through decode logic modules. This dimensional change in the information distribution architecture reduces the number of latches required and enables more efficient parallel testing and repair operations.

The patent merges the repair information storage function into a compact repair register that combines multiple repair control signals into a single register structure. This merging approach reduces the total number of latches required compared to having separate latch structures for each repair control signal, while still enabling comprehensive repair operations across multiple memory arrays.

The repair register serves multiple functions: it stores select bits for identifying defective elements, stores repair actions for different types of repairs, and provides control signals for both single array and multiple array repair operations. This multi-functionality reduces the need for separate latch structures for each function, thereby reducing the overall latch count.

The patent implements local repair capability at each memory array through distributed decode logic modules that can independently generate and execute repair operations for defective elements within each array. This local quality approach allows each array to be repaired independently without requiring global redundancy, thereby maintaining high test efficiency while providing effective repair capability for defective elements.

Each memory array is equipped with its own decode logic modules that can autonomously generate repair signals based on defect detection, enabling self-service repair operations. This eliminates the need for external control latches and reduces overall system complexity while maintaining the ability to repair defects effectively, thus preventing yield loss without sacrificing test efficiency.