Microcode Sequencer BIST for Memory Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity and cost of testing semiconductor memory devices, particularly Dynamic Random Access Memory (DRAM) with large capacities and varied types, due to incomplete testing at the wafer level and challenges in connecting memory devices to testers, necessitates a flexible and efficient Built-In Self Test (BIST) solution that supports wafer, packaged part, and system testing.
Innovation Solution
A small and flexible BIST capability integrated into memory devices, utilizing reprogrammable microcode sequencers for performing memory tests and generating command operations, with a simple test interface that allows testing at full clock rates and supports pattern sensitivity tests, implemented through a BIST controller, test-load controller, and data checker, enabling serial or parallel data loading and unloading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If custom BIST designs are used to provide flexible testing capabilities, then adaptability to different testing scenarios is improved, but device complexity increases
Solution Approach 1:
The BIST controller is designed to perform multiple testing functions including pattern sensitivity tests, data retention tests, and march tests through a unified microcode sequencer architecture. The same hardware infrastructure supports wafer-level testing, packaged part testing, and system-level testing, eliminating the need for separate custom designs for each testing scenario.
Solution Approach 2:
The microcode sequencer provides dynamic reconfigurability by loading different test algorithms through serial or parallel data loading. The BIST controller can adapt its behavior based on the loaded microcode, allowing flexible testing capabilities without requiring complex hardwired logic for each specific test type.
2Reliability
If comprehensive memory testing is performed at wafer level, then manufacturing quality is improved, but testing cost and complexity increase
Solution Approach 1:
The memory device performs self-testing through the integrated BIST controller that generates test patterns, applies them to the memory array, and checks results without requiring external testing equipment. The memory device tests itself using its own internal resources including memory cells, bit lines, and word lines, significantly reducing external testing complexity.
Solution Approach 2:
The BIST controller merges multiple testing functions into a single integrated unit that combines pattern generation, test execution, and result verification. The test-load controller and data checker are combined with the microcode sequencer to create a unified testing subsystem that reduces overall system complexity compared to separate testing components.
3Measurement precision
If detailed testing algorithms are implemented to cover pattern sensitivities and data retention, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The testing algorithm is segmented into distinct microcode routines that can be independently loaded and executed. Pattern sensitivity tests, data retention tests, and march tests are separated into different microcode sequences, allowing precise implementation of each test type while managing complexity through modular organization of test logic.
Solution Approach 2:
The microcode sequencer acts as an intermediary between the simple hardware BIST controller and the complex testing algorithms. It translates high-level test requirements into specific control signals for the memory device, enabling detailed testing without requiring complex hardwired logic in the BIST controller itself.
Data Source
AI summary
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into a main microcode sequencer and loading subroutine instructions into a subroutine microcode sequencer on the memory. The microcode instructions generate subroutine calls to the subroutine microcode sequencer. The subroutine instructions generate memory operation codes, address codes, and data codes for testing a memory device. BIST addresses are generated in response to the memory operation codes and the address codes. BIST data are generated in response to the memory operation codes and the data codes. Conventional memory commands are created by generating command signals, address signals, and data signals for the memory in response to the memory operation codes, the BIST data, and the BIST addresses. Test results output data may be stored in a data checker in the form of information stored in data registers or checksum registers.