Microcode Load Mechanism Using Inter Processor Interrupt Messages
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Solution Overview
Problem
The increasing number of cores in information handling systems leads to inefficiencies in microcode loading, particularly during power-on self-test (POST) operations, due to the need for individual microcode loading on each core, resulting in prolonged resume times and increased bus cycles.
Innovation Solution
A method involving a broadcast inter-process interrupt (IPI) message is used to synchronize microcode across multiple cores within a processor system, allowing microcode to be loaded efficiently without independent loading on each core, thereby reducing the time required for microcode loading and simplifying BIOS operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microcode is loaded independently to each core during power-on self test, then each core can execute its required microcode, but the resume time increases proportionally with the number of cores
Solution Approach 1:
The patent merges the microcode loading process across multiple cores by having the BIOS load microcode to only one core (the first core) and then using an inter-processor interrupt (IPI) message to broadcast and synchronize the microcode to all other cores. This combining approach reduces the total loading time while ensuring all cores receive the necessary microcode.
Solution Approach 2:
The patent applies preliminary action by loading the microcode to the first core in advance before triggering the IPI broadcast. This allows the microcode to be prepared and ready for distribution to other cores, reducing the overall resume time during power-on self test.
2Reliability
If microcode is loaded independently to each core, then each core has its microcode, but the bus cycle overhead increases with the number of cores
Solution Approach 1:
The patent merges multiple separate microcode loading operations into a single loading operation followed by an IPI broadcast. Instead of each core independently fetching microcode from memory (which would generate multiple bus cycles), the system performs one load and then uses the IPI mechanism to distribute the microcode, significantly reducing bus cycle overhead.
3Productivity
If the number of cores increases, then processing capacity increases, but the time to wake up and load microcode to each core increases proportionally
Solution Approach 1:
The patent merges the microcode loading process into a single operation that serves all cores simultaneously through the IPI broadcast mechanism. This allows the system to maintain high processing capacity with increased core counts while the microcode loading time does not increase proportionally, as all cores receive the microcode through the broadcast rather than requiring individual loading sequences.
Data Source
AI summary
A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core. The synchronizing loads microcode to the plurality of cores without requiring independent loads of microcode to each core.