Microcode-Based Memory Controller for Flash Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory controllers face challenges in balancing complexity and extendibility while maintaining high performance, particularly in efficiently controlling multiple flash memories, with hard-wired logic being complex and inflexible, and firmware-based designs being simpler but lower in performance.
Innovation Solution
A memory system with a top control sequencer and channel control sequencers that utilize microcodes to control memory devices, where the host processor generates and transfers microcodes to execute operations, reducing the load on the host processor and allowing for adaptability to changing specifications by modifying the microcodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hard-wired logic memory controller is used to control instruction sequences of flash memory, then performance is improved, but device complexity increases and extendibility is limited
Solution Approach 1:
The patent introduces a microcode-based intermediary layer between the host processor and flash memory devices. The memory controller executes microcode instructions that act as intermediaries to manage complex flash memory operations, thereby improving performance without directly hard-wiring the controller logic. This intermediary microcode layer handles the complexity internally while presenting a simpler interface to the host.
Solution Approach 2:
The patent changes the control parameter from fixed hard-wired logic to programmable microcode instructions. By storing control sequences as microcode in memory rather than hard-wiring them, the system can dynamically change control parameters through software updates, improving both performance and extendibility while reducing design complexity.
2Adaptability or versatility
If a firmware-based memory controller is used to control instruction sequences of flash memory, then device complexity is reduced and extendibility is improved, but performance decreases
Solution Approach 1:
The patent segments the control functionality into multiple components: a top control sequencer for high-level coordination and channel control sequencers for device-specific operations. This segmentation allows the system to maintain simplicity and extendibility through modular firmware while achieving high performance through specialized microcode routines for each segment.
Solution Approach 2:
The patent implements preliminary action by pre-loading microcode instructions into the control sequencers before execution. The microcode is generated by the host processor and transferred to the memory controller in advance, allowing the controller to execute optimized instruction sequences without real-time processing overhead, thus improving performance while maintaining firmware-based flexibility.
3Productivity
If a memory controller is designed to efficiently control multiple flash memories, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent implements universality through a top control sequencer that manages multiple channel control sequencers, each capable of controlling different flash memory devices. This multi-functional architecture allows a single controller design to efficiently manage multiple flash memories with varying specifications through a unified microcode-based control mechanism, improving productivity without proportionally increasing complexity.
Data Source
AI summary
Provided are a memory system and a method of driving the same. The method includes setting microcodes in a top control sequencer and multiple channel control sequencers, and executing the microcode set in the top control sequencer. The method may further include checking execution results of the microcode.