Microcode Patch Remaps Cache Flush to Mitigate Side-Channel Attacks
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Solution Overview
Problem
Existing solutions for mitigating flush plus reload cache side-channel attacks are invasive, complex, and require changes to CPU hardware, impacting performance and storage, and are not compatible with existing CPUs.
Innovation Solution
Implementing a microcode patch that remaps cache flush instructions to cache write back instructions, preventing attackers from influencing access timing by retaining non-modified cache lines, thus defeating the flush plus reload attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing solutions for mitigating flush plus reload cache side-channel attacks are implemented, then security against side-channel attacks is improved, but CPU performance and storage are impacted, and compatibility with existing CPUs is lost
Solution Approach 1:
The patent changes the behavior parameter of the CLFLUSH instruction by introducing a microcode patch that remaps it to CLWB functionality. This parameter change allows the instruction to maintain cache lines instead of flushing them, thereby preventing side-channel attacks while preserving CPU performance and storage characteristics of the original instruction
2Reliability
If existing solutions for mitigating flush plus reload cache side-channel attacks are implemented, then security against side-channel attacks is improved, but device complexity increases due to hardware changes and zombie cache line tracking
Solution Approach 1:
The patent creates a functional copy of the cache flush operation through microcode that remaps the CLFLUSH instruction to CLWB behavior. This copying approach allows the system to simulate the desired security effect without modifying the actual hardware architecture or introducing complex tracking mechanisms for zombie cache lines
3Reliability
If existing solutions for mitigating flush plus reload cache side-channel attacks are implemented, then security against side-channel attacks is improved, but ease of manufacture and deployment is worsened due to incompatibility with existing CPUs
Solution Approach 1:
The patent introduces microcode as an intermediary layer between the instruction set architecture and the hardware execution units. This intermediary allows existing x86 CPUs to execute the patched CLFLUSH instruction with modified behavior without requiring any hardware modifications, thereby maintaining full compatibility with existing processors while implementing the security mitigation
Data Source
AI summary
Systems and methods related to flush plus reload cache side-channel attack mitigation are described. An example method for mitigating a side-channel timing attack in a system including a processor having at least one cache is described. The method includes receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The method further includes, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.