Microcode Patch Mechanism for On-Chip Memory Overlay
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Solution Overview
Problem
Existing microcode patch techniques in microprocessors introduce pipeline delays and are inflexible, limiting performance and flexibility, especially when implementing one-to-many patches or loading patches during fabrication.
Innovation Solution
A microcode patch mechanism using a fuse array to store patches, a patch loader to provide patches to designated mechanisms, and an expansion RAM to execute patches without impacting processor throughput, allowing for real-time one-to-one and one-to-many microcode patches without pipeline delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional microcode patch techniques are used, then patches can be applied to correct errors, but pipeline delays are introduced and performance is impacted
Solution Approach 1:
The patent applies preliminary action by pre-loading patch data into dedicated patch storage locations (such as patch RAM or overlay memory) before the actual patching operation is needed. This allows the patch mechanism to retrieve and apply corrections without interrupting the main instruction pipeline, thereby maintaining throughput while enabling error correction. The patch data is prepared in advance in a separate buffer, so when a patch is required, it can be applied quickly without stalling the pipeline.
Solution Approach 2:
The patent introduces an intermediary patch storage mechanism between the microcode ROM and the instruction execution unit. This intermediate layer (patch RAM, overlay memory, or cache) acts as a buffer that holds patch data temporarily. The intermediary allows the main instruction stream to continue executing while patch operations occur in the background or are applied from this buffer, decoupling the patching process from the critical instruction pipeline and preventing throughput degradation.
2Adaptability or versatility
If flexible patch mechanisms are implemented, then one-to-many patches and real-time patching are enabled, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the patch mechanism into distinct functional modules: a fuse array for storing patch identification data, a patch loader for retrieving and processing patches, and dedicated patch storage locations (patch RAM or overlay memory) for holding patch data. This modular segmentation allows each component to perform its specific function independently, making the overall system more manageable and easier to implement while providing flexible one-to-many patching capabilities. The segmentation also enables parallel operation of multiple patch functions without mutual interference.
Solution Approach 2:
The patent implements universality by designing a multi-functional patch mechanism that can handle various patch types and scenarios through a single integrated system. The fuse array and patch loader work together to support both one-to-one and one-to-many patching operations, as well as real-time patching during execution. This universal design allows the same basic architecture to serve multiple purposes (error correction, performance optimization, debugging) without requiring separate dedicated circuits for each function, thereby reducing overall complexity despite the enhanced versatility.
3Ease of manufacture
If patches are loaded during fabrication, then initial configuration is enabled, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by incorporating a fuse array that can be programmed during the semiconductor fabrication process. The fuse array stores patch identification data and configuration information that are set once during manufacturing. This allows the microprocessor to be pre-configured with specific patch capabilities or default patch data without requiring complex post-fabrication programming procedures. The fuse programming is performed as part of the standard fabrication flow, making it an integrated rather than additive complexity to the manufacturing process.
Data Source
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AI summary
A patch mechanism in a microprocessor is provided. The patch mechanism includes an expansion RAM and a patch loader. The expansion RAM stores a plurality of patches, where a first one or more of the plurality of patches are to be executed by the microprocessor in place of a corresponding one or more micro instructions which are stored in a microcode ROM, and where a second one or more of the plurality of patches are employed to patch a corresponding one or more machine states in the microprocessor. The patch loader is coupled to the expansion RAM, and is configured to retrieve the plurality of patches from a source external to the microprocessor, and is configured to load the plurality of patches into the expansion RAM.