Microcode Patching via Sequestered Cache Sections
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Solution Overview
Problem
Current methods for updating processor microcode require replacing the processor for minor bugs or enhancements, which is costly and unwieldy, and existing microcode patching solutions are not efficiently integrated with the Unified Extensible Firmware Interface (UEFI) phases.
Innovation Solution
The solution involves a data processing system with a cache memory that sequesters cache sections to store and execute processor microcode, using a Firmware Interface Table (FIT) to manage microcode patches, and implementing a process that loads and authenticates microcode during the UEFI phases, allowing for secure and efficient patching without replacing the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor microcode is updated by replacing the processor, then reliability and error correction are improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent creates a copy of the microcode in a sequestered cache section rather than replacing the physical processor. The original microcode resides in the processor, and a patched version is loaded into cache memory, allowing updates without hardware replacement. This copying approach maintains reliability improvements while avoiding the complexity of processor replacement.
Solution Approach 2:
The sequestered cache section acts as an intermediary between the original processor microcode and the patched microcode version. It holds the patched microcode in isolation, allowing the system to execute corrected code without physically replacing the processor, thus improving reliability while reducing device complexity.
2Adaptability or versatility
If processor microcode is patched using traditional methods, then feature enhancements and bug fixes are achieved, but integration with UEFI phases is inefficient
Solution Approach 1:
The patent performs microcode patching during the SEC phase of UEFI initialization, before the system fully boots. By sequestering cache sections and loading patched microcode in advance during the security phase, the system prepares the patched microcode beforehand, improving integration efficiency with UEFI phases while maintaining adaptability.
Solution Approach 2:
The patent divides the cache memory into sequestered sections specifically for microcode storage, separating microcode management from other system operations. This segmentation allows efficient handling of microcode patches during UEFI phases without interfering with other system functions, improving both adaptability and productivity.
3Ease of manufacture
If cache memory is used to store patched microcode, then processor replacement is avoided and cost is reduced, but cache memory management complexity increases
Solution Approach 1:
The system automatically manages the sequestered cache sections for microcode storage without requiring external intervention. The firmware autonomously identifies, allocates, and manages cache sections for microcode, reducing the need for complex external cache management mechanisms while maintaining cost-effectiveness by avoiding processor replacement.
4Reliability
If microcode is authenticated during UEFI phases, then security is improved, but boot time and initialization duration increase
Solution Approach 1:
The patent performs microcode authentication during the SEC phase, which occurs early in the UEFI initialization process. By authenticating microcode beforehand during the security phase rather than later during DXE or BDS phases, the system ensures security while minimizing the impact on overall boot time, as authentication occurs during mandatory security checks anyway.
Data Source
AI summary
Methods and systems for performing microcode patching are presented. In one embodiment, a data processing system comprises a cache memory and a processor. The cache memory comprises a plurality of cache sections. The processor sequesters one or more cache sections of the cache memory and stores processor microcode therein. In one embodiment, the processor executes the microcode in the one or more cache sections.