Microcomputer Bus Controller Frequency Conversion Logic
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Solution Overview
Problem
Current microcomputer systems face limitations in allowing bus access between bus masters and slaves due to frequency mismatches, leading to decreased cycle performance and inflexible arbitration in situations with multiple bus access requests, particularly when bus slaves operate at lower frequencies than bus masters.
Innovation Solution
A microcomputer design that includes a CPU with variable frequency clock and a timer with a separate clock frequency, utilizing a bus controller with frequency conversion logic to generate bus control signals based on synchronization signals, enabling bus access regardless of the frequency relationship between the CPU and timer, and incorporating a write buffer to manage access order and arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock domain conversion is performed with synchronization signal to enable communication between bus masters and bus slaves, then communication between different frequency domains is achieved, but frequency constraints limit the ability to freely combine frequencies of bus master and bus slave
Solution Approach 1:
The patent applies dynamics by making the bus controller's operation mode changeable based on frequency relationships. The bus controller can switch between first operation mode (when CPU frequency > timer frequency) and second operation mode (when CPU frequency < timer frequency), allowing the system to adapt to different frequency combinations while maintaining reliable bus access through appropriate synchronization mechanisms for each mode.
2Productivity
If write buffer is used to improve cycle performance, then write access speed is improved, but access order control becomes complex requiring dummy read operations to guarantee ordering
Solution Approach 1:
The patent uses the bus controller as an intermediary that manages the write buffer operations. The bus controller receives write access requests from the CPU, controls the write buffer, and coordinates with the timer to ensure proper access ordering. This intermediary approach allows the write buffer to improve cycle performance while the bus controller handles the complexity of maintaining access order through controlled buffering and timing.
3Reliability
If arbitration is performed in accordance with predetermined order of priority, then bus access conflict is resolved, but flexible arbitration cannot be performed in situations requiring substantially no cycle performance
Solution Approach 1:
The patent applies dynamics to arbitration by making the arbitration logic changeable based on operational conditions. The bus controller can switch between first arbitration logic (for normal operations with predetermined priority) and second arbitration logic (for situations requiring flexible arbitration with substantially no cycle performance). This allows the system to maintain reliable conflict resolution while adapting to different performance requirements through dynamic arbitration strategy selection.
Data Source
AI summary
Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus. Therefore, bus access can be gained irrespective of the magnitude relationship between the frequencies of the CPU and timer.