Microcomputer Memory Interface Circuit Layout for Miniaturization
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Solution Overview
Problem
The miniaturization of microcomputer chips with memory interface circuits is limited by the size constraints, leading to increased correlation between circuit positions and characteristics, which can result in reliability issues and challenges in high-density line arrangements on module boards.
Innovation Solution
The microcomputer design features memory interface circuits positioned along the peripheries of a rectangular semiconductor board, with data and data strobe signal units separated to reduce size limitations and allow for easier connection with various memory types, including 8-bit and 16-bit interfaces, while also optimizing line routes and power supply configurations to enhance reliability and noise resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip size is reduced through miniaturization, then the compactness and integration density are improved, but the number of available I/O cells is limited and circuit correlation increases leading to reliability deterioration
Solution Approach 1:
The memory interface circuit is divided into multiple independent functional blocks (data input unit, data output unit, command input unit, command output unit, address input unit, address output unit) that are spatially separated on the chip. This segmentation allows each block to be optimized independently and reduces signal correlation between different interface functions, thereby maintaining reliability in miniaturized designs.
Solution Approach 2:
The patent transitions from a conventional planar arrangement to a three-dimensional stacked architecture where memory devices are arranged in multiple layers above the substrate. This vertical dimensionality change increases storage capacity and interface density without increasing the chip footprint, effectively decoupling size reduction from functionality loss.
2Object-affected harmful factors
If data and data strobe signal pin arrays are separated according to JEDEC standard, then noise resistance is improved, but the interface width requirement increases to 7 mm or larger
Solution Approach 1:
The patent employs a three-dimensional stacked memory architecture where multiple memory devices are vertically arranged above the substrate. This vertical stacking enables the memory system to achieve high storage capacity and wide interface functionality without increasing the lateral footprint, effectively resolving the conflict between noise-resistant signal separation and compact chip size.
3Length of stationary object
If a rectangular chip with longer sides of 7 mm or larger is used to accommodate the interface, then the interface signal can be disposed, but the correlation between circuit positions and characteristics increases
Solution Approach 1:
The memory interface circuit is divided into multiple independent functional blocks (data input unit, data output unit, command input unit, command output unit, address input unit, address output unit) that are spatially separated on the chip. This segmentation allows each block to be optimized independently and reduces signal correlation between different interface functions, thereby maintaining reliability in miniaturized designs.
4Quantity of substance
If high-density line arrangement is implemented on module board, then packaging density is improved, but testability and noise resistance become challenging
Solution Approach 1:
The memory interface circuit is divided into multiple independent functional blocks (data input unit, data output unit, command input unit, command output unit, address input unit, address output unit) that are spatially separated on the chip. This segmentation allows each block to be optimized independently and reduces signal correlation between different interface functions, thereby maintaining reliability in miniaturized designs.
Data Source
AI summary
A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.