Microcomputer Memory Protection Register Invalidation

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Solution Overview

Problem

Conventional microcomputers face issues with memory protection reliability due to failure in rewriting protection setting registers when switching programs, leading to potential unauthorized memory accesses and execution problems.

Innovation Solution

A microcomputer with a CPU, protection information storage, memory access control, and a reset apparatus that invalidates past memory protection information before updating it for newly executed programs, ensuring accurate memory access control and improved reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory protection information is rewritten when switching programs, then memory access control is improved, but reliability deteriorates due to potential failure in rewriting protection setting registers

Engineering Contradiction:
Improvememory access control reliabilityVSAvoidresidual memory protection information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent applies preliminary action by invalidating the valid bits in protection setting registers before rewriting memory protection information when switching programs. This ensures that residual information from previous programs cannot affect the new program's memory access control, preventing potential security issues while maintaining reliable program switching.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If memory protection information is rewritten when switching programs, then adaptability is improved, but reliability deteriorates due to potential rewriting failures

Engineering Contradiction:
Improveprogram switching capabilityVSAvoidmemory protection reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system performs preliminary invalidation of protection setting registers before program switching, ensuring that the memory protection mechanism is in a known good state before being reconfigured for the new program. This maintains adaptability for program switching while improving reliability by preventing partial or failed rewrites from compromising security.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If protection setting registers are sequentially rewritten, then device complexity is reduced, but reliability deteriorates due to potential omission of rewriting

Engineering Contradiction:
Improvememory protection completenessVSAvoidprotection setting mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a preliminary invalidation step that sets all valid bits to invalid before rewriting protection information. This simple preparatory action ensures that even if the sequential rewriting process fails or is incomplete, residual information cannot compromise the new program's memory protection, thereby improving reliability without significantly increasing complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9904631B2Microcomputer and method for controlling memory access
Publication Date: 2018.02.27 RENESAS ELECTRONICS CORP
  • US9904631B2 patent drawing
  • US9904631B2 patent drawing
  • US9904631B2 patent drawing

AI summary

A memory control system includes a memory connected to a memory bus, the memory including a plurality of access areas, a memory controller connected to the memory bus, a plurality of registers corresponding to the plurality of access areas, each of the plurality of registers configured to set an access permission or prohibition for a corresponding access area, a CPU (Central Processing Unit) configured to issue a first access request for accessing one of the plurality of access areas, and a memory access controller configured to determine whether an access to the memory is permissible or prohibited using the first access request and the plurality of registers, the memory access controller outputting a second access request in accordance with a determination result.